Design of voltage scaled level converters in low power clock distribution networks

Rajesh, A.; Raju, B. L.; Reddy, K. Chenna Kesava

doi:10.1109/rteict.2016.7807888

Cited by 1 publication

(1 citation statement)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Dynamic voltage frequency scaling (DVFS) and adaptive voltage scaling are the most effective techniques for power reduction, which function with a design that operates at different voltage modes [4]. Level converters are used in those designs to save power and improve speed [5]. To handle clocking strategies in the DVFS, the separate clock trees were generated for different operating modes.…”

Section: Related Workmentioning

confidence: 99%

An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts

Srinath¹,

Verma

Barnawi

et al. 2021

Electronics

View full text Add to dashboard Cite

Managing the timing constraints has become an important factor in the physical design of multiple supply voltage (MSV) integrated circuits (IC). Clock distribution and module scheduling are some of the conventional methods used to satisfy the timing constraints of a chip. In this paper, we propose a simulated annealing-based MSV floorplanning methodology for the design of ICs within the timing budget. Additionally, we propose a modified SKB tree representation for floorplanning the modules in the design. Our algorithm finds the optimal dimensions and position of the clocked modules in the design to reduce the wirelength and satisfy the timing constraints. The proposed algorithm is implemented in IWLS 2005 benchmark circuits and considers power, wirelength, and timing as the optimization parameters. Simulation results were obtained from the Cadence Innovus digital system taped-out at 45 nm. Our simulation results show that the proposed algorithm satisfies timing constraints through a 30.6% reduction in wirelength.

show abstract

Section: Related Workmentioning

confidence: 99%