SUMMARYA modification has been introduced to the new superconvergent patch derivative recovery technique recently developed (Zienkiewicz and Zhu, 1991). By use of a locally normalized co-ordinate system, the application of this technique can now be applied to higher-order finite-element shape functions. Numerical studies are carried out for up to 6th-order elements in one dimension and for up to quartic elements in two dimensions, and superconvergent results are obtained for all examples tested.
In sub-100 nm nodes, continuously shrinking CD imposes more demanding requirement on wafer planarity to satisfy constrains of diminishing DOF of lithography process. However, due to incoming non-planarity of wafer surface caused by ECP, and inherent removal rate selectivity regarding to dielectric and metal films of CMP slurries, post Cu-CMP topography exhibits strong dependency not only on process conditions, but also on layout pattern of processed wafers. In this paper, such layout pattern-dependency of post Cu-CMP topography was studied with a pre-designed test chip. Post CMP Cu line thickness and area array-height were characterized with respect to metal line width and feature pattern density. Semi-empirical models were built based on multivariate response surface methodology (RSM) to simulate post Cu-CMP surface topography. By applying the developed models, post CMP Cu-line thickness and area array height were predicted across a shot of M1 layer of a typical 40 nm logic product. The prediction is verified by TEM cross section for selected features. Potential risky hotspots were successfully highlighted by the models.
Modern market requires smaller products with more functionalities which are driven by high speed Package Circuit Boards (PCBs) and Integrated Circuit (IC) packages. Thermal control of PCBs and IC packages is challenging in microelectronics because the power density increases when smaller and more complicated packages are designed. Temperature rise due to power dissipation, hotspot worsens harmful clock skew, jeopardizes reliability of products. To overcome these risks, PCBs and IC packages designers have to perform electromagnetic-thermal co-simulations at the early design stage. Usually the temperature rise of the whole package is easy to be calculated, it is difficult to detect the hotspots in the package due to local high current density because very high resolution simulations are needed. In this paper, an improved adaptive finite element method (FEM) is applied to detect hotspots. This method only requires one step adaptive refinements in every FEM solution for a given error threshold in the hotspot detection progress, so that it is very fast and uses much smaller computation resources. Test results show that the adaptive FEM only uses about 60 times memory and CPU time to detect all hotspots in the package comparing to the initial FEM solution.
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