In sub-100 nm nodes, continuously shrinking CD imposes more demanding requirement on wafer planarity to satisfy constrains of diminishing DOF of lithography process. However, due to incoming non-planarity of wafer surface caused by ECP, and inherent removal rate selectivity regarding to dielectric and metal films of CMP slurries, post Cu-CMP topography exhibits strong dependency not only on process conditions, but also on layout pattern of processed wafers. In this paper, such layout pattern-dependency of post Cu-CMP topography was studied with a pre-designed test chip. Post CMP Cu line thickness and area array-height were characterized with respect to metal line width and feature pattern density. Semi-empirical models were built based on multivariate response surface methodology (RSM) to simulate post Cu-CMP surface topography. By applying the developed models, post CMP Cu-line thickness and area array height were predicted across a shot of M1 layer of a typical 40 nm logic product. The prediction is verified by TEM cross section for selected features. Potential risky hotspots were successfully highlighted by the models.
Electronic Copper Plating (ECP) topography is known affected by layout design and dummy inserting. With different electroplate liquid, copper can be filled in the trench by the forms of conformal-fill, bottom-up or supper-fill. Such post ECP topography not only depends on process conditions, but also exhibits strong pattern-related dependency. Here, pattern-related effects of ECP topography were characterized with a pre-designed test chip that contains test-keys of line/space arrays of varying line and space widths, and varying pattern-density (PD). It was shown that: 1) Fixed PD at 50%, the characteristics of test features array height (AH) and Step-height (SH) are strongly associated with line-width (LW). 2) Fixed LW, different trends were observed for narrow lines and wide lines, in both AH and SH vs. varying PD. A semi-empirical model was built to simulate post-ECP topography. It captured all key pattern-dependency in post-ECP AH and SH with acceptable fitting GOF (R2>90%).
As a front-end technology, shallow trench isolation ( STI ) is widely used in submicron nodes of IC manufacturing because of its high space utilization rate on device layout. Chemical mechanical polishing (CMP) is used to achieve planarization by polishing off the oxide on top of pad nitride in a STI structure. When STI-CMP process is completed, oxide in the trench would likely form dish-shaped structure (dishing), which negatively affects the process stability and device performance. Such negative effect becomes more significant when IC technology advancing to nanometer nodes. Thus dishing improvement in STI-CMP for nanometer technology attracts more and more attention. In this paper, we studied influences of polishing amounts, CMP pressure and some other factors on post STI-CMP dishing performance in 45/40nm node. It was concluded that increasing in oxide polishing amount can reduce dishing; decreasing polishing pressure can enhance robustness of endpoint detection but has negligible effects on dishing reduction.
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