In this study, a method to test blind TSVs in 3D IC integration for their electrical performance is investigated. Emphasis is placed on the development of a novel blind-TSV method by electrical testing on the top side of the TSV-wafer before backgrinding. Through leakage current testing, it is possible to determine whether there is short circuit between blind TSVs. Most conventional measurement methods can only be performed after wafer thinning to reveal the TSVs Cu and/or backside processing, which could lead to a higher manufacturing cost of 3D IC integration products if the electrical performances of the manufactured TSV don't meet the specification.Also, by providing analysis flow of high frequency simulation and measurement, we can define the thickness of the isolation layer (Silicon dioxide, SiO 2 ) of blind TSV into specification. Furthermore, the analysis flow can obtain the important high-frequency parameter of silicon material such as silicon conductivity. Finally, the SEM images of cross sections verify the current findings.
The feasibility of a 3D IC integration SiP has been demonstrated in this investigation. The heart of this SiP is a TSV (through-silicon via) interposer with RDL (redistribution layer) on both sides, IPD (integrated passive devices) and SS (stress sensors). This interposer is used to support (with microbumps) a stack of four memory chips with TSVs, one thermal chip with heater and one mechanical chip with SS, and then overmolded on its top side for pick and place purposes. The interposer’s bottom-side is attached to an organic substrate (with ordinary lead-free solder bumps), which is lead-free solder-balled on a PCB (printed circuit board). Key enabling technologies such as TSV etching, chemical mechanical polishing (CMP), thin-wafer handling, thermal management, and microbumping, assembly and reliability are highlighted.
In this investigation, a system-in-package (SiP) that consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top and bottom sides (a real 3-D IC integration) is studied. Emphasis is placed on the fabrication of a test vehicle to demonstrate the feasibility of this SiP technology. The design, materials, and process of the top chip, bottom chip, TSH interposer, and final assembly will be presented. Shock and thermal cycling tests will be performed to demonstrate the integrity of the SiP structure.
In this study, a very low-cost silicon interposer with many through-silicon holes (TSHs) for 3D IC integration system-inpackage (SiP) applications is proposed. Unlike TSVs (through-silicon vias), the uniqueness of this design is there is not the dielectric layer, barrier layer, seed layer, filled Cu, and thus CMP and TSV Cu reveal are not necessary for the TSHs. The vertical interconnects between (face-to-face) the top chips and bottom chips of the TSH interposer are through Cu wires or columns. The electrical, thermal and mechanical behaviors of this new design are demonstrated by nonlinear finite element simulations.
This paper proposes a 3D IC integration TSV testing apparatus, primarily using at least one set of TSV component testing devices with a specific design. Under complex technological conditions, such as varying depth-width ratios of TSVs and heterogeneous IC integration, as well as the principle of different coupling parasitic parameters between TSVs, the TSV coupling measuring device designed for specific purposes in coordination with a measuring method for high-frequency coupling TSV S-parameters, achieving the function of monitoring the SiO2 thickness of TSVs. This feasible approach further allows judgment of whether subsequent processes can continue, effectively reducing costs.
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