Electrical testing of blind Through-Silicon Via (TSV) for 3D IC integration

Abstract

In this study, a method to test blind TSVs in 3D IC integration for their electrical performance is investigated. Emphasis is placed on the development of a novel blind-TSV method by electrical testing on the top side of the TSV-wafer before backgrinding. Through leakage current testing, it is possible to determine whether there is short circuit between blind TSVs. Most conventional measurement methods can only be performed after wafer thinning to reveal the TSVs Cu and/or backside processing, which could lead to a higher manufacturing cost of 3D IC integration products if the electrical performances of the manufactured TSV don't meet the specification.Also, by providing analysis flow of high frequency simulation and measurement, we can define the thickness of the isolation layer (Silicon dioxide, SiO 2 ) of blind TSV into specification. Furthermore, the analysis flow can obtain the important high-frequency parameter of silicon material such as silicon conductivity. Finally, the SEM images of cross sections verify the current findings.

Fabrication and characterization of a low-cost interposer with an intact insulation layer and ultra-low TSV leakage current

“…Under the bias voltage of 30 V, TSV leakage current for pitch = 220 and 1000 μm are 1.43 × 10 −13 and 1.00 × 10 −14 A, respectively. This is much lower than the usual value in the range of 10 −12 -10 −9 A [11,19,29]. This ultra-low leakage current indicates a high-quality TSV insulation layer of the interposer.…”

Study of TSV leakage current and breakdown voltage

“…Theoretically, the isolation layer couldn't be absolutely non-conductive; hence it would bring about leakage current between the TSVs when DC voltages were added on [4]. Owing to the higher density and smaller pitch of TSVs on the wafer, the leakage current problem is becoming more and more serious.…”

Supply chains for 3D IC integration manufacturing

“…It can be seen from Figures 2 to 7 that, there are many important tasks in the MEOL (solder bumping / temporary bonding / backgrinding / TSV Cu revealing / thin wafer handling / de-bonding / cleaning), assembly and test; thus the OSAT should strive to make themselves ready for a robust and high yield manufacturing process. In order to avoid finger pointing and have a smooth hand-off from the FAB to OSAT of the un-finished (blind) TSV wafers, more research and development works should be performed on the testing methods of the blind TSV wafers for electrical, for example [20,21], thermal, for example [22], and mechanical performances.…”