Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300mm Multi-Project Wafer (MPW)

Abstract

The feasibility of a 3D IC integration SiP has been demonstrated in this investigation. The heart of this SiP is a TSV (through-silicon via) interposer with RDL (redistribution layer) on both sides, IPD (integrated passive devices) and SS (stress sensors). This interposer is used to support (with microbumps) a stack of four memory chips with TSVs, one thermal chip with heater and one mechanical chip with SS, and then overmolded on its top side for pick and place purposes. The interposer’s bottom-side is attached to an organic substrate (with ordinary lead-free solder bumps), which is lead-free solder-balled on a PCB (printed circuit board). Key enabling technologies such as TSV etching, chemical mechanical polishing (CMP), thin-wafer handling, thermal management, and microbumping, assembly and reliability are highlighted.

Recent Advances and New Trends in Nanotechnology and 3D Integration for Semiconductor Industry

“…Also, stress sensors are implanted on the top side and IPDs (integrated passive devices) are fabricated through the thickness (100μm) of the interposer (12.3mm x 12.2mm). Figure 6 shows the assembled test vehicle and Figure 7 shows the SEM image of a cross section and the x-ray image of a portion of the SiP [20]. Even the assembly is not perfect yet, however it is not so bad for the first time.…”

“…(5.1) Interposer Used as Intermediate Substrate Today, the most well-known interposer is in Xilinx's FPGA wide I/O interface [15][16][17][18], which has been mentioned in section (4.5). Figure 5 shows a cross section of ITRI's 3D IC integration SiP test vehicle [19], which consists of an interposer supporting four memory chips, one thermal chip, and one mechanical chip. It is over molded for pick-and-place purpose as well as protecting the chips from harsh environments.…”

“…This test vehicle can be degenerated to the case of: (a) wide I/O memory if there is not the memory-chip stacking nor the TSVs in the mechanical/thermal chips and the interposer is either an logic, microprocessor, or SoC; (b) wide I/O DRAM if there are not mechanical and thermal chips and the interposer is a logic chip; and (c) wide I/O interface if there is not the memory-chip stacking and there is not any TSV in the thermal/ mechanical chips. Thus, the core enabling technologies (such as via etching, dielectric, barrier and seed layers deposition, via filling, CMP, thin-wafer handling, electrical and thermal design and test of TSVs, wafer bumping of ultra finepitch lead-free microbumps, fluxless C2W bonding, electronmigration of microbumps, and reliability of microbump assemblies) developed [19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36] with this test vehicle are very useful and can have very broad applications. surrounding Si as shown in Figure 9.…”

Supply chains for 3D IC integration manufacturing

“…Next is chip-to-wafer (C2W) bonding, for example [18,19], i.e., the micro bumped memory chip is bonded (either by natural reflow or thermal compression) to the TSV wafer with the carrier. After face-to-back C2W bonding, the carrier wafer is debonded from the TSV wafer.…”

Electrical testing of blind Through-Silicon Via (TSV) for 3D IC integration

“…Comparing to other interconnection technologies such as the wire bonding, the advantages of TSV are [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19]:…”