An Electrical Testing Method for Blind Through Silicon Vias (TSVs) for 3D IC Integration

Abstract

This paper proposes a 3D IC integration TSV testing apparatus, primarily using at least one set of TSV component testing devices with a specific design. Under complex technological conditions, such as varying depth-width ratios of TSVs and heterogeneous IC integration, as well as the principle of different coupling parasitic parameters between TSVs, the TSV coupling measuring device designed for specific purposes in coordination with a measuring method for high-frequency coupling TSV S-parameters, achieving the function of monitoring the SiO2 thickness of TSVs. This feasible approach further allows judgment of whether subsequent processes can continue, effectively reducing costs.

Recent Advances and New Trends in Nanotechnology and 3D Integration for Semiconductor Industry

“…This test vehicle can be degenerated to the case of: (a) wide I/O memory if there is not the memory-chip stacking nor the TSVs in the mechanical/thermal chips and the interposer is either an logic, microprocessor, or SoC; (b) wide I/O DRAM if there are not mechanical and thermal chips and the interposer is a logic chip; and (c) wide I/O interface if there is not the memory-chip stacking and there is not any TSV in the thermal/ mechanical chips. Thus, the core enabling technologies (such as via etching, dielectric, barrier and seed layers deposition, via filling, CMP, thin-wafer handling, electrical and thermal design and test of TSVs, wafer bumping of ultra finepitch lead-free microbumps, fluxless C2W bonding, electronmigration of microbumps, and reliability of microbump assemblies) developed [19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36] with this test vehicle are very useful and can have very broad applications. surrounding Si as shown in Figure 9.…”