In the past decade, solution-based dielectric oxides have been widely studied in electronic applications enabling the use of low-cost processing technologies and device improvement. The most promising are the high-κ dielectrics, like aluminum (AlO) and hafnium oxide (HfO), that allow an easier trap filling in the semiconductor and the use of low operation voltage. However, in the case of HfO, a high temperature usually is needed to induce a uniform and condensed film, which limits its applications in flexible electronics. This paper describes how to obtain HfO dielectric thin films and the effect of their implementation in multilayer dielectrics (MLD) at low temperatures (150 °C) to apply in thin film transistors (TFTs) using the combination of solution combustion synthesis (SCS) and ultraviolet (UV) treatment. The single layers and multilayers did not show any trace of residual organics and exhibited a small surface roughness (<1.2 nm) and a high breakdown voltage (>2.7 MV·cm). The resulting TFTs presented a high performance at a low operation voltage (<3 V), with high saturation mobility (43.9 ± 1.1 cm·V·s), a small subthreshold slope (0.066 ± 0.010 V·dec), current ratio of 1 × 10 and a good idle shelf life stability after 2 months. To our knowledge, the results achieved surpass the actual state-of-the-art. Finally, we demonstrated a low-voltage diode-connected inverter using MLD/IGZO TFTs working with a maximum gain of 1 at 2 V.

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A novel CMOS device architecture called silicon on nothing (SON) is proposed, which allows extremely thin (in the order of a few nanometers) buried dielectrics and silicon films to be fabricated with high resolution and uniformity guarantied by epitaxial process. The SON process allows the buried dielectric (which may be an oxide but also an air gap) to be fabricated locally in dedicated parts of the chip, which may present advantages in terms of cost and facility of system-on-chip integration. The SON stack itself is physically confined to the under-gate-plus-spacer area of a device, thus enabling extremely shallow and highly doped extensions, while leaving the HDD (highly doped drain) junctions comfortably deep. Therefore, SON embodies the ideal device architecture taking the best elements from both bulk and SOI and getting rid of their drawbacks. According to simulation results, SON enables excellent Ion/Ioff trade-off, suppressed self-heating, low S/D series resistance, close to ideal subthreshold slope, and high immunity to SCE and DIBL down to ultimate device dimensions of 30 to 50 nm.

The current trend for smart, self-sustainable, and multifunctional technology demands for the development of energy harvesters based on widely available and environmentally friendly materials. In this context, ZnSnO 3 nanostructures show promising potential because of their high polarization, which can be explored in piezoelectric devices. Nevertheless, a pure phase of ZnSnO 3 is hard to achieve because of its metastability, and obtaining it in the form of nanowires is even more challenging. Although some groups have already reported the mixing of ZnSnO 3 nanostructures with polydimethylsiloxane (PDMS) to produce a nanogenerator, the resultant polymeric film is usually flat and does not take advantage of an enhanced piezoelectric contribution achieved through its microstructuration. Herein, a microstructured composite of nanowires synthesized by a seed-layer free hydrothermal route mixed with PDMS (ZnSnO 3 @PDMS) is proposed to produce nanogenerators. PFM measurements show a clear enhancement of d 33 for single ZnSnO 3 versus ZnO nanowires (23 ± 4 pm/V vs 9 ± 2 pm/V). The microstructuration introduced herein results in an enhancement of the piezoelectric effect of the ZnSnO 3 nanowires, enabling nanogenerators with an output voltage, current, and instantaneous power density of 120 V, 13 μA, and 230 μW·cm –2 , respectively. Even using an active area smaller than 1 cm 2 , the performance of this nanogenerator enables lighting up multiple LEDs and other small electronic devices, thus proving great potential for wearables and portable electronics.

Semiconductor nanowires are mostly processed by complex, expensive, and high temperature methods. In this work, with the intent of developing zinc tin oxide nanowires (ZTO NWs) by low-cost and low-complexity processes, we show a detailed study on the influence of chemical parameters in the hydrothermal synthesis of ZTO nanostructures at temperatures of only 200 °C. Two different zinc precursors, the ratio between zinc and tin precursors, and the concentration of the surfactant agent and of the mineralizer were studied. The type and the crystallinity of the nanostructures were found to be highly dependent on the used precursors and on the concentration of each reagent. Conditions for obtaining different ZTO nanostructures were achieved, namely, Zn 2 SnO 4 nanoparticles and ZnSnO 3 nanowires with length ∼600 nm, with the latter being reported for the first time ever by hydrothermal methods without the use of seed layers. Optical and electrical properties were analyzed, obtaining band gaps of 3.60 and 3.46 eV for ZnSnO 3 and Zn 2 SnO 4 , respectively, and a resistivity of 1.42 kΩ·cm for single ZnSnO 3 nanowires, measured using nanomanipulators after localized deposition of Pt electrodes by e-beam assisted gas decomposition. The low-temperature hydrothermal methods explored here proved to be a low-cost, reproducible, and highly flexible route to obtain multicomponent oxide nanostructures, particularly ZTO NWs. The diversity of the synthesized ZTO structures has potential application in next-generation nanoscale devices such as field effect nanotransistors, nanogenerators, resistive switching memories, gas sensors, and photocatalysis.

The impact of a parylene top-coating layer on the illumination and bias stress instabilities of indium-gallium-zinc oxide thin-film transistors (TFTs) is presented and discussed. The parylene coating substantially reduces the threshold voltage shift caused by continuous application of a gate bias and light exposure. The operational stability improves by 75%, and the light induced instability is reduced by 35%. The operational stability is quantified by fitting the threshold voltage shift with a stretched exponential model. Storage time as long as 7 months does not cause any measurable degradation on the electrical performance. It is proposed that parylene plays not only the role of an encapsulation layer but also of a defect passivation on the top semiconductor surface. It is also reported that depletion-mode TFTs are less sensitive to light induced instabilities. This is attributed to a defect neutralization process in the presence of free electrons.

This paper presents a study concerning the role of channel length scaling on IGZO TFT technology benchmark parameters, which are fabricated at temperatures not exceeding 180 • C. The parameters under investigation are unity currentgain cutoff frequency, intrinsic voltage-gain, and on-resistance of the bottom-gate IGZO TFTs. As the channel length varies from 160 to 3 μm, the measured cutoff frequency increases from 163 kHz to 111.5 MHz, which is a superior value compared to the other competing low-temperature thin-film technologies, such as organic TFTs. On the other hand, for the same transistor dimensions, the measured intrinsic voltage-gain is changing from 165 to 5.3 and the on-resistance is decreasing from 1135.6 to 26.1 kΩ. TFTs with smaller channel length (3 μm) have shown a highly negative turnon voltage and hump in the subthreshold region, which can be attributed to short channel effects. The results obtained here, together with their interpretation based on device physics, provide crucial information for accurate IC design, enabling an adequate selection of device dimensions to maximize the performance of different circuit building blocks assuring the multifunctionality demanded by system-on-panel concepts. Index Terms-Intrinsic voltage-gain, unity current-gain cutoff frequency, IGZO TFTs and channel length scaling. I. INTRODUCTION I NDIUM-GALLIUM-ZINC oxide thin-film transistors (IGZO TFTs) are becoming a reference technology for flexible, ultra-definition or even transparent display backplanes.

of less destructive switching events, since the device reliability is independent of the reproducibility of the filament formation. [6] Frequently, an analog switching is observed, which is applicable for neuromorphic systems. [7][8][9][10] Reports exist in the literature, which explore area-dependent switching involving the homogeneous migration of defects or ions through the thickness of the switching matrix. [11,12] This can be referred to as 3D RS. In a device with asymmetric electrodes, both 1D RS and 3D RS result in counter eightwise (c8w) switching loops, when the bias is applied to the current blocking electrode. [13] Another type of area-dependent RS exists when ions are exchanged (or trapping occurs at the interface) between the switching matrix and the electrode. If the current transport through this interface is modulated as a consequence of the ion exchange/trapping, then this can be referred to as 2D RS. The direction of the switching loops is opposite to 1D RS and 3D RS, that is, eightwise (8w) when the bias is applied to the current blocking electrode. Frequently, 2D volatile switching has been observed as a secondary process, affecting the high resistive state (HRS) of an otherwise 1D RS device. [14][15][16][17] In addition, the choice between digital and analog operation modes by different device initialization schemes has been reported for NiO-based devices. [18] However, the resistance window for the analog mode was below one order of magnitude and the mechanism was discussed as 3D RS.Both in 3D RS and 2D RS, the active interface represents a barrier to the current flow, for example, a Schottky junction. [19] In the case of Ti/Pr 0.7 Ca 0.3 MnO 3 (PCMO) devices the underlying mechanism is based on a redox reaction between the titanium oxide interlayer and the PCMO. [20,21] In oxide-based devices with a platinum Schottky barrier bottom electrode, electronic trapping at interface states was proposed as a mechanism. [15] To allow a sizeable data retention, structural stabilization of the trapped charge needs to occur. [22] To achieve a high ratio between HRS and low resistance state (LRS) in 3D and 2D RS, a highly mobile Fermi level, that is, a highly variable charge carrier concentration is desirable. In thin-film transistors (TFT), AOS are known to yield tremendously high on/off ratios. [23] Diodes of AOS have rectification ratios of 10 6 . [24] These applications show how the material is able to change from an insulator to a metallic conductor by A room-temperature-processed resistive switching Schottky diode that can be operated in two distinct modes, depending solely on the choice of device initialization mode, is presented. Electroforming in the diode's reverse polarity leads to an abrupt filamentary switching with inherently long data retention at the expense of rectification. After this electroforming process, the devices may work in either a bipolar or unipolar manner with a resistance window of at least two orders of magnitude. Device initialization in the forward direction shows a smoo...