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display backplanes and creating multifunctional flexible circuitry with thin-film technologies are considered. Within this scenario, amorphous oxide semiconductor (AOS) became one of the most competitive TFT technologies, enabling excellent uniformity in large areas, high transparency in visible spectrum, and field-effect mobility (µ FE ) exceeding 10 cm 2 V −1 s −1 even when fabricated below 200 °C. [1][2][3] The potential of these materials as semiconductors in TFTs started to be recognized in 2004 with the work by Nomura et al. on flexible indium-gallium-zinc oxide (IGZO) transistors. [4] Despite the establishment of IGZO TFTs as a key technology for large-area electronics, indium and gallium are critical raw materials, imposing important constrains regarding the sustainability of this approach. [5] Therefore, the ideal route for the next-generation AOS-based transistor technology should comprise an indium-and gallium-free semiconductor material, providing at least comparable performance and processing temperature to IGZO. Zinc-tin oxide (ZTO) has been recognized as a likely choice. Chiang et al. [6] reported in 2005 the first successful integration of sputtered ZTO as semiconductor layer in TFTs. Their staggered bottom-gate, top contact devices showed µ FE ≈ 20-50 cm 2 V −1 s −1 , turn-on voltage (V on ) between −5 and 5 V, and on/off ratio > 10 7 when annealed at 600 °C. However, µ FE drastically decreased to 5-15 cm 2 V −1 s −1 when lower annealing temperature (300 °C) was used, which is still too high for temperature-sensitive polymeric substrates as polyethylene naphthalene (PEN). Since then more than 150 articles on ZTO TFTs have been published, following both physical and solution-processing routes. Focusing on sputtering, which is the processing technique with easier penetration on an industrial TFT baseline process, aspects as different Zn:Sn ratios, [7][8][9] chamber pressure, oxygen flow ratio, and RF power during sputtering have been studied. [10] Nonetheless, for all these experiments a processing or post-processing temperature exceeding 300 °C was always used to achieve proper device operation (e.g., µ FE > 5 cm 2 V −1 s −1 in devices properly patterned, where overestimation of mobility due to fringing effects can be neglected. [11] A very recent work by Han et al. [12] is the exception to this, where a remarkable saturation mobility (µ sat ) of 67 cm 2 V −1 s −1 is achieved for polycrystalline tin-doped Zinc-tin oxide (ZTO) is widely invoked as a promising indium and galliumfree alternative for amorphous oxide semiconductor based thin-film transistors (TFTs). The main bottleneck of this semiconductor material compared to mainstream indium-gallium-zinc oxide (IGZO) is centered in the larger processing temperatures required to achieve acceptable performance (>300 °C), not compatible with low-cost flexible substrates. This work reports for the first time flexible amorphous-ZTO TFTs processed at a maximum temperature of 180 °C. Different aspects are explored to obtain performance levels comparable ...

This paper presents a study concerning the role of channel length scaling on IGZO TFT technology benchmark parameters, which are fabricated at temperatures not exceeding 180 • C. The parameters under investigation are unity currentgain cutoff frequency, intrinsic voltage-gain, and on-resistance of the bottom-gate IGZO TFTs. As the channel length varies from 160 to 3 μm, the measured cutoff frequency increases from 163 kHz to 111.5 MHz, which is a superior value compared to the other competing low-temperature thin-film technologies, such as organic TFTs. On the other hand, for the same transistor dimensions, the measured intrinsic voltage-gain is changing from 165 to 5.3 and the on-resistance is decreasing from 1135.6 to 26.1 kΩ. TFTs with smaller channel length (3 μm) have shown a highly negative turnon voltage and hump in the subthreshold region, which can be attributed to short channel effects. The results obtained here, together with their interpretation based on device physics, provide crucial information for accurate IC design, enabling an adequate selection of device dimensions to maximize the performance of different circuit building blocks assuring the multifunctionality demanded by system-on-panel concepts. Index Terms-Intrinsic voltage-gain, unity current-gain cutoff frequency, IGZO TFTs and channel length scaling. I. INTRODUCTION I NDIUM-GALLIUM-ZINC oxide thin-film transistors (IGZO TFTs) are becoming a reference technology for flexible, ultra-definition or even transparent display backplanes.

topic along the last decade. [1][2][3][4] Paper's basic unit is cellulose, which is the most abundant biopolymer on earth; it is a lowcost material (≈10 −3 cent m −2 ), lightweight, flexible, and 100% recyclable. Moreover, the nearly 100 million tons produced per year using roll-to-roll processing with speed of about 30 m s −1 turns paper and cellulose-based materials highly attractive to serve the pushing demands for the new era of low-cost disposable and recyclable large area electronics for concepts such as Internet-of-Things (IoT), with a strong future societal impact. [5][6][7][8][9][10] From the commercial point of view, the use of paper in "electronics" has been mostly limited to separator membranes in passive electronic components such as capacitor batteries, or simply as a substrate for hybrid radio-frequency identification (RFID) tags. Even if still looking for real market implantation, it has been demo nstrated that paper can also be used as a platform for microfluidics and sensors, energy storage devices, organic thin film transistors (OTFTs), printed batteries, or even foldable printed circuit boards. [11][12][13] The exploration of paper as a genuinely electronic material has been demonstrated for the first time in our past work, where it was used as gate dielectric in field effect transistors (FETs), [9,[14][15][16] write-erase and read memory transistors (WERM-FETs), [17] solidstate paper batteries, [18] and inverters. [19] These reports demonstrate that paper offers an eclectic range of applications as substrate or as an active part in devices, enabling a new generation of low-cost and disposable analogue and digital electronic circuits. [20] In this work, we go further in exploring paper as the gate dielectric by implementing it on dual-gate in-plane oxide-based FETs with a back floating gate electrode (DG-FGFETs) enabling multilogic functionalities. Although the concept of dual-gate FET has been already tested on Si technology with SiO 2 -based gate dielectrics, [21,22] it is now proposed on paper, which is simultaneously explored as the substrate and solid-state electrolyte relying on the electric double layer (EDL) formation. This concept has also been used with organic semiconductors on paper surfaces, [21] and even with other ionic dielectrics, as chitosan or alginate, to create artificial synapses to emulate biological synaptic functions, which are often referred to as synaptic transistors in the literature. [22,23] However, the on-voltage (V On ) modulation through the second gate and the ability to perform logic operations with these devices has not been thoroughly reported using oxides Electronics on paper enable some specific applications out of conventional ones which require innovative approaches and concepts on the design of devices and systems. Within this context, this work demonstrates that a unique set of characteristics can be combined in planar dual-gate oxide-based field effect transistors with a back floating electrode using paper simultaneously as substrate and dielectric. ...

Novel nature‐based engineered functional materials combined with sustainable and economically efficient processes are among the great challenges for the future of mankind. In this context, this work presents a new generation of versatile flexible and highly conformable regenerated cellulose hydrogel electrolytes with high ionic conductivity and self‐healing ability, capable of being (re)used in electrical and electrochemical devices. They can be provided in the form of stickers and easily applied as gate dielectric onto flexible indium–gallium–zinc oxide transistors, decreasing the manufacturing complexity. Flexible and low‐voltage (<2.5 V) circuits can be handwritten on‐demand on paper transistors for patterning of conductive/resistive lines. This user‐friendly and simplified manufacturing approach holds potential for fast production of low‐cost, portable, disposable/recyclable, and low‐power ion‐controlled electronics on paper, making it attractive for application in sensors and concepts such as the “Internet‐on‐Things.”

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This paper characterizes transparent current mirrors with n-type amorphous gallium-indium-zinc-oxide (a-GIZO) thin-film transistors (TFTs). Two-TFT current mirrors with different mirroring ratios and a cascode topology are considered. A neural model is developed based on the measured data of the TFTs and is implemented in Verilog-A; then it is used to simulate the circuits with Cadence Virtuoso Spectre simulator. The simulation outcomes are validated with the fabricated circuit response. These results show that the neural network can model TFT accurately, as well as the current mirroring ability of the TFTs.Index Terms-Transparent current mirrors, amorphous gallium-indium-zinc-oxide thin-film transistor (a-GIZO TFT), neural modeling.

This paper focuses on the analysis of InGaZnO thin-film transistors (TFTs) and circuits under the influence of different temperatures and bias stress, shedding light into their robustness when used in real-world applications. For temperature-dependent measurements, a temperature range of 15 to 85 °C was considered. In case of bias stress, both gate and drain bias were applied for 60 min. Though isolated transistors show a variation of drain current as high as 56% and 172% during bias voltage and temperature stress, the employed circuits were able to counteract it. Inverters and two-TFT current mirrors following simple circuit topologies showed a gain variation below 8%, while the improved robustness of a cascode current mirror design is proven by showing a gain variation less than 5%. The demonstration that the proper selection of TFT materials and circuit topologies results in robust operation of oxide electronics under different stress conditions and over a reasonable range of temperatures proves that the technology is suitable for applications such as smart food packaging and wearables.