We demonstrate herein an effective method of forming a high-quality contact between metal and graphene on a wafer as large as 6 in. This gold-assisted transfer method producing no polymer residue on the graphene surface is introduced, and then the gold film is used directly as an electrode to form the transfer length method pattern for calculating the contact resistance. The graphene surface obtained using the gold-assisted transfer method is clean and uniform without residue or contamination, and its contact resistance is at least 60% lower than that obtained using the conventional poly(methyl methacrylate) assisted transfer method.

The origins of the high device performance and degradation in the air are the greatest issues for commercialization of perovskite solar cells. Here this study investigates the possible origins of the mixed perovskite cells by monitoring defect states and compositional changes of the perovskite layer over the time. The results of deep‐level transient spectroscopy analysis reveal that a newly identified defect formed by Br atoms exists at deep levels of the mixed perovskite film, and its defect state shifts when the film is aged in the air. The change of the defect state is originated from loss of the methylammonium molecules of the perovskite layer, which results in decreased JSC, deterioration of the power conversion efficiency and long‐term stability of perovskite solar cells. The results provide a powerful strategy to diagnose and manage the efficiency and stability of perovskite solar cells.

We present a novel method for fabricating large-area field-effect transistors (FETs) based on densely packed multichannel graphene nanoribbon (GNR) arrays using advanced direct self-assembly (DSA) nanolithography. The design of our strategy focused on the efficient integration of the FET channel and using fab-compatible processes such as thermal annealing and chemical vapor deposition. We achieved linearly stacked DSA nanopattern arrays with sub-10 nm half-pitch critical dimensions (CD) by controlling the thickness of topographic Au confinement patterns. Excellent roughness values (∼10% of CD) were obtained, demonstrating the feasibility of integrating sub-10 nm GNRs into commercial semiconductor processes. Based on this facile process, FETs with such densely packed multichannel GNR arrays were successfully fabricated on 6 in. silicon wafers. With these high-quality GNR arrays, we achieved FETs showing the highest performance reported to date (an on-to-off ratio larger than 10(2)) for similar devices produced using conventional photolithography and block-copolymer lithography.

A partial etching mechanism is proposed to meet the requirement for low-visibility patterning of silver nanowire (AgNW)-based transparent conductive electrodes (TCEs) by reducing the difference in optical properties between conductive and nonconductive regions of the pattern. Using the finite difference time domain (FDTD) method, etched geometries that provide the smallest difference in transmittance after etching are theoretically determined. A sodium hypochlorite-based etchant capable that allows the etched geometry to be varied by controlling the pH is used to create a low-visibility pattern with a transmittance and haze difference of 0.07 and 0.04%, respectively. To the best of our knowledge, this is the first time that a partial etching mechanism such as this has been studied in relation to AgNW-based TCEs.