Self-Aligned Multichannel Graphene Nanoribbon Transistor Arrays Fabricated at Wafer Scale

Abstract

We present a novel method for fabricating large-area field-effect transistors (FETs) based on densely packed multichannel graphene nanoribbon (GNR) arrays using advanced direct self-assembly (DSA) nanolithography. The design of our strategy focused on the efficient integration of the FET channel and using fab-compatible processes such as thermal annealing and chemical vapor deposition. We achieved linearly stacked DSA nanopattern arrays with sub-10 nm half-pitch critical dimensions (CD) by controlling the thickness of topographic Au confinement patterns. Excellent roughness values (∼10% of CD) were obtained, demonstrating the feasibility of integrating sub-10 nm GNRs into commercial semiconductor processes. Based on this facile process, FETs with such densely packed multichannel GNR arrays were successfully fabricated on 6 in. silicon wafers. With these high-quality GNR arrays, we achieved FETs showing the highest performance reported to date (an on-to-off ratio larger than 10(2)) for similar devices produced using conventional photolithography and block-copolymer lithography.

PMMA-Assisted Plasma Patterning of Graphene

“…e structural change was noticeable by light microscopy and verified by Raman spectroscopy (Figure 3). An increase in the magnitude of the D peak (∼1300 cm ), in the Raman characteristic of graphene ribbons (Figure 3) with respect to that of pristine graphene (Figure 1), agrees with previous reports on the patterning of graphene ribbons; that is, the increase in the D peak is obtained during the process of patterning [15,44,45].…”

“…Han [8] reported a I max /I min value around ∼1.6 (V g � 0-20 V dc ) for graphene ribbon with widths of 49 and 71 nm at 200 K. While Jeong et al [45] reported a I max /I min value of ∼3.1 (V g � 0-20 V dc ) for an array of graphene ribbons with sub-10 nm width at room temperature. In the present report, the I max /I min is around ∼1.4 (V g � 0-20 V dc ) for graphene ribbons with width of 50 or 100 nm at room temperature.…”

Graphene Nanoribbons for Electronic Devices

“…Different approaches for the fabrication of GNRs have been developed during the past ten years. As shown in Figure , the wide portfolio includes -Patterning of large‐area graphene, which, in turn, is obtained by either mechanical exfoliation of graphene flakes from graphite crystals, graphene CVD (chemical vapor deposition) growth on metals and subsequent transfer to insulating substrates, or sublimation of Si (silicon) from a SiC (silicon carbide) surface (epitaxial graphene) 2,8]. -Chemical synthesis from precursors -Unzipping CNTs (carbon nanotube) by chemical processes …”

“…A widely used method for patterning large‐area graphene is etching using a mask which may consist of a resist pattern defined by e‐beam (electron beam) lithography, pre‐deposited nanowires (e.g., chemically synthesized Si nanowires),) or self‐assembled BCP (block copolymer) nanopatterns . GNRs have also been directly written without a mask by lithography based on STM (scanning tunneling microscopy), AFM (atomic force microscopy), and TEM (transmission electron microscopy) .…”

Photoluminescent Arrays of Nanopatterned Monolayer MoS2

“…Thin films of BCPs thus enable nanoscale patterning of various materials including silicon, silicon nitride, and metal oxides for use in air–gap structures, capacitors, field effect transistors, memories, and other devices . In particular, BCPs have been used to pattern graphene into nanoribbons with sub‐10 nm widths for use in transistors, quantum dots, as well as hexagonal nanomesh . Thin films of BCPs have been employed in templating the growth of 3D crystalline nanoparticles and nanowires of TMDs .…”