Macrobenthos of the deep, northern Gulf of Mexico (GoM) was sampled with box cores (0.2 m 2 ) along multiple cross-depth transects extending from depths of 200 m to the maximum depth of the basin at 3700 m. Bathymetric (depth) zonation of the macrofaunal community was documented for 6 major taxa (a total of 957 species) on the basis of shared species among geographic locations; 4 major depth zones were identified, with the 2 intermediatedepth zones being divided into east and west subzones. Change of faunal composition with depth reflects an underlying continuum of species replacements without distinct boundaries. The zonal patterns correlated with depth and detrital particulate organic carbon (POC) export flux estimated from remotely-sensed phytoplankton pigment concentrations in the surface water. The Mississippi River and its associated mesoscale eddies, submarine canyon, and deep sediment fan appear to influence the horizontal zonation pattern through export of organic carbon from the ocean surface and the adjacent continental margin. On the local scale, near-bottom currents may shape the zonation pattern by altering sediment grain size, food availability, and larval dispersal. This study suggests a macroecological relationship between depth, export POC flux, and zonation; parsimonious zonal thresholds need to be tested independently for other continental margin ecosystems.KEY WORDS: Northern Gulf of Mexico · Deep sea · Macrofauna · Zonation · Biogeography · Community structure · POC export flux · Macroecology Resale or republication not permitted without written consent of the publisherThaumastasoma species 521 (Crustacea; Isopoda; Nannoniscidae), a typical species of the lower continental slope.

The capability and heterogeneity of new FPGA (Field Programmable Gate Array) devices continues to increase with each new line of devices. Efficiently programming these devices is increasing in difficulty. However, FPGAs continue to be utilized for algorithms traditionally targeted to embedded DSP microprocessors such as signal and image processing applications.This paper presents an architecture that combines VLIW (Very Large Instruction Word) processing with the capability to introduce application specific customized instructions and complex hardware functions. To support this architecture, a compilation and design automation flow are described for programs written in C.Several design tradeoffs for the architecture were examined including number of VLIW functional units and register file size. The architecture was implemented on an Altera Stratix II FPGA. The Stratix II device was selected because it offers a large number of high-speed DSP (digital signal processing) blocks that execute multiply accumulate operations.We show that our combined VLIW with hardware functions exhibit as much as 230X speedup and 63X on average for computational kernels for a set of benchmarks. This allows for an overall speedup of 30X and 12X on average for signal processing benchmarks from the MediaBench.

This paper presents an architecture that combines VLIW (very long instruction word) processing with the capability to introduce application-specific customized instructions and highly parallel combinational hardware functions for the acceleration of signal processing applications. To support this architecture, a compilation and design automation flow is described for algorithms written in C. The key contributions of this paper are as follows: (1) a 4-way VLIW processor implemented in an FPGA, (2) large speedups through hardware functions, (3) a hardware/software interface with zero overhead, (4) a design methodology for implementing signal processing applications on this architecture, (5) tractable design automation techniques for extracting and synthesizing hardware functions. Several design tradeoffs for the architecture were examined including the number of VLIW functional units and register file size. The architecture was implemented on an Altera Stratix II FPGA. The Stratix II device was selected because it offers a large number of high-speed DSP (digital signal processing) blocks that execute multiply-accumulate operations. Using the MediaBench benchmark suite, we tested our methodology and architecture to accelerate software. Our combined VLIW processor with hardware functions was compared to that of software executing on a RISC processor, specifically the soft core embedded NIOS II processor. For software kernels converted into hardware functions, we show a hardware performance multiplier of up to 230 times that of software with an average 63 times faster. For the entire application in which only a portion of the software is converted to hardware, the performance improvement is as much as 30X times faster than the nonaccelerated application, with a 12X improvement on average.

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