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The capability and heterogeneity of new FPGA (Field Programmable Gate Array) devices continues to increase with each new line of devices. Efficiently programming these devices is increasing in difficulty. However, FPGAs continue to be utilized for algorithms traditionally targeted to embedded DSP microprocessors such as signal and image processing applications.This paper presents an architecture that combines VLIW (Very Large Instruction Word) processing with the capability to introduce application specific customized instructions and complex hardware functions. To support this architecture, a compilation and design automation flow are described for programs written in C.Several design tradeoffs for the architecture were examined including number of VLIW functional units and register file size. The architecture was implemented on an Altera Stratix II FPGA. The Stratix II device was selected because it offers a large number of high-speed DSP (digital signal processing) blocks that execute multiply accumulate operations.We show that our combined VLIW with hardware functions exhibit as much as 230X speedup and 63X on average for computational kernels for a set of benchmarks. This allows for an overall speedup of 30X and 12X on average for signal processing benchmarks from the MediaBench.

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This study analyzed the environmental impacts of the materials phase of a net-zero energy building. The Center for Sustainable Landscapes (CSL) is a three-story, 24,350 square foot educational, research, and administrative office in Pittsburgh, PA, USA. This net-zero energy building is designed to meet Living Building Challenge criteria. The largest environmental impacts from the production of building materials is from concrete, structural steel, photovoltaic (PV) panels, inverters, and gravel. Comparing the LCA results of the CSL to standard commercial structures reveals a 10% larger global warming potential and a nearly equal embodied energy per square feet, largely due to the CSL's PV system. As a net-zero energy building, the environmental impacts associated with the use phase are expected to be very low relative to standard structures. Future studies will incorporate the construction and use phases of the CSL for a more comprehensive life cycle perspective.

DRAM technology scaling has the undesirable side effect of degrading cell reliability.

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