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High-performance FinFET SONOS (silicon-oxide-nitrideoxide-silicon) flash cells with gate length down to 20nm have been fabricated and operated successfully on bulk-silicon substrate for the first time. A program/erase window of 2V has been achieved with high P/E speed (T P = 10µs and T E = 1ms), and a 1.5V window remained after 10 years at room temperature. Multi-level storage is also obtained with ∆V t > 4V and T P,E = 1ms. Operation voltages are not more than 7V in the two applications. Gate disturb issues are alleviated by applying an appropriate bias on unselected bit lines.

We have, for the first time, experimentally quantified random dopant distribution (RDD) induced V t standard deviation up to 40mV for 20nm-gate planar CMOS. Discrete dopants have been statistically positioned in the 3D channel region to examine associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". As gate length further scaling down to 15nm, the newly developed discrete-dopant scheme features an effective solution to suppress 3-sigma-edge single digit dopants induced V t variation by gate work function modulation. The extensive study may postpone the scaling limit projected for planar CMOS.

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Performance gain arising from 40nm/0.7GPa tensile contact-etch-stop layer has been significantly amplified from intrinsic 6% up to 15% by newly developed Stress Intermedium Engineering (SIE) technology. A stress transfer model considering mechanical properties of intermedium materials is proposed to account for the performance boost. Neither worse short-channel effects nor abnormal junction leakage were found with the SIE technology. Excellent gate oxide integrity and hot carrier immunity of the SIE technology have also been verified for manufacture implementation. This study features a new paradigm of channel strain engineering for sub-65nm CMOS scaling, in addition to conventional approach of stressor optimization.