Discrete Dopant Fluctuations in 20-nm/15-nm-Gate Planar CMOS

Li, Yiming; Yu, Shao-Ming; Hwang, Jiunn-Ren; Yang, Fu-Liang

doi:10.1109/ted.2008.921991

Cited by 105 publications

(75 citation statements)

References 19 publications

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“…Notably, the mobility model activated in our device simulation considers the influence of surface orientations on the on-state current by the term of effective electric field for every fin angle [16]. The mobility model is quantified with our recent device measurements for the best accuracy of simulation, and the characteristic fluctuation has been validated with the experimentally measured DC base band data from 15/20 CMOS devices [15]. For each statistical device simulation, 216 RDfluctuated FinFET devices are randomly generated for every fin angle to estimate the magnitude of the RDFinduced characteristic fluctuation.…”

Section: Methodsmentioning

confidence: 99%

Electrical characteristic fluctuation of 16-nm-gate trapezoidal bulk FinFET devices with fixed top-fin width induced by random discrete dopants

Huang¹,

Li²

2016

Nano Online

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In this work, we use an experimentally calibrated 3D quantum mechanically corrected device simulation to study the random dopant fluctuation (RDF) on DC characteristics of 16-nm-gate trapezoidal bulk fin-type field effect transistor (FinFET) devices. The fixed top-fin width, which is consistent with the realistic process by lithography, of trapezoidal bulk FinFET devices is considered in this study. For RDF on trapezoidal bulk FinFETs under the fixed top-fin width, we explore the impact of geometry and RDF on the on-/off-state current and the threshold voltage (V th ) fluctuation with respect to different channel fin angles. For the same channel doping concentration, compared with an ideal FinFET (i.e., device with a right angle of channel fin), the off-state current is large in trapezoidal bulk FinFETs with a small fin angle. Furthermore, the short-channel effect and V th variation degrade as the fin angle is getting smaller. The magnitude of the normalized σV th increases 7% when the fin angle decreases from 90°to 70°.

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Section: Methodsmentioning

confidence: 99%

Electrical characteristic fluctuation of 16-nm-gate trapezoidal bulk FinFET devices with fixed top-fin width induced by random discrete dopants

Huang¹,

Li²

2016

Nano Online

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“…Many researchers have investigated the effects of random dopant fluctuation on transistor performance using various approaches: (1) an analytical approach [22], (2) an atomistic process simulation using Kinetic Monte Carlo (KMC) simulation [23,24], (3) a naïve approach [25], and (4) a full three-dimensional (3-D) TCAD simulation with randomized doping profiles [26][27][28][29]. In order to provide insight into random dopant fluctuation, two primary factors should be considered: (1) the number of dopant atoms, and (2) the positions of the given dopant atoms.…”

Section: Characterization Of Random Dopant Fluctuation (Rdf)mentioning

confidence: 99%

Random Dopant Fluctuation (RDF)

Shin

2016

Variation-Aware Advanced CMOS Devices and SRAM

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Following Moore's Law [1], semiconductor industries have doubled the density of transistors in integrated circuits (ICs) every two years. This has rapidly increased the performance of ICs because the degree of integration has grown exponentially. However, below the 1 μm technology node, a serious technical issue was encountered that frustrated further shrinking of the gate pitch, namely, the short channel effect (SCE) [2,3]. The short channel effect brings about other undesirable effects, such as threshold voltage (V TH ) roll off [4-6] and drain-induced barrier lowering (DIBL) [7][8][9]. As the portion of the channel region depleted by the source/drain junction increases as much as the channel length is shortened, the threshold voltage is reduced. In other words, lower gate voltage is required to invert the channel region because a larger part of the channel region is already depleted by the source/ drain-to-channel junctions. The second phenomenon, namely, drain-induced barrier lowering (DIBL), occurs when the source-to-channel potential barrier is affected by the drain bias. If the gate length of metal oxide semiconductor field effect transistors (MOSFETs) is scaled down to such an extent that the energy barrier height at the source-to-channel interface is decreased because of the electric field emanating from the drain region, more electrons can diffuse from the source to the drain over the energy barrier at the source/channel interface. This causes higher off-state leakage current, degraded subthreshold slope, and a lowered threshold voltage. In order to alleviate short channel effects, the channel region of MOSFETs should be sufficiently doped to minimize (i) the depletion charge induced by the source/drain junction, and (ii) the impact of drain bias on the modulation of the height of the energy barrier at the source/channel interface [10]. In very scaled MOSFETs in sub-32 nm technology nodes, the doping concentration in the channel (or the halo doping concentration) is close to 10 18 cm −3 or even higher [11,12].

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“…There are a few approaches to understanding the effect of the RDF on the total V TH variation: (i) atomistic process simulation using the Kinetic Monte Carlo simulator [18], (ii) naïve approach [19], and (iii) full three-dimensional (3-D) TCAD simulation with randomized doping profiles [20]. The average number of dopants in the atomistic region of the MOSFETs can be calculated by integrating the continuously distributed doping profiles in the MOSFETs.…”

Section: Random Dopant Fluctuation (Rdf)mentioning

confidence: 99%

Analysis of Random Variations and Variation-Robust Advanced Device Structures

Nam¹,

Lee²,

Lee³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (V TH ) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted siliconon-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmentedchannel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.

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Discrete Dopant Fluctuations in 20-nm/15-nm-Gate Planar CMOS

Cited by 105 publications

References 19 publications

Electrical characteristic fluctuation of 16-nm-gate trapezoidal bulk FinFET devices with fixed top-fin width induced by random discrete dopants

Electrical characteristic fluctuation of 16-nm-gate trapezoidal bulk FinFET devices with fixed top-fin width induced by random discrete dopants

Random Dopant Fluctuation (RDF)

Analysis of Random Variations and Variation-Robust Advanced Device Structures

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