20nm gate bulk-finFET SONOS flash

Abstract

High-performance FinFET SONOS (silicon-oxide-nitrideoxide-silicon) flash cells with gate length down to 20nm have been fabricated and operated successfully on bulk-silicon substrate for the first time. A program/erase window of 2V has been achieved with high P/E speed (T P = 10µs and T E = 1ms), and a 1.5V window remained after 10 years at room temperature. Multi-level storage is also obtained with ∆V t > 4V and T P,E = 1ms. Operation voltages are not more than 7V in the two applications. Gate disturb issues are alleviated by applying an appropriate bias on unselected bit lines.

Numerical simulation of vertical tunnelling field-effect transistors charge-trapping memory with TCAD tools

“…Jang et al [13] demonstrated the vertical NAND flash memory array by TCAT technology with metal gate structure, which leads to good P/E characteristics and reliability for multi-level cell operation. Jiunn-Ren et al [14] fabricate high-performance FinFET SONOS flash cells with gate length down to 20 nm on bulk-silicon substrate with high P/E speed. Lue et al [15] presented a novel p-channel NAND-Flash memory using nitride-trapping device, with an ultra-thin bandgap engineered ONO tunnelling dielectric is adopted to achieve efficient hole-tunnelling erase at high electric field, but yet good data retention at low field.…”

Novel junctionless silicon–oxide–nitride–oxide–silicon memory devices with field-enhanced poly-Si nanowire structure

“…Thus, a new type of flash memory based on charge trapping, namely, the silicon-oxide-nitrideoxide-silicon (SONOS) memory, has been widely studied. [1][2][3][4] This type of memory can easily overcome the gate coupling problem, can be more immune to the defects in the tunnel oxide, and can also be more scalable owing to the smaller gate stack height for gate control. The flash memory constructed on thin film transistors (TFTs) has several advantages such as a low-cost and low-temperature fabrication process, and possible applications in systemon-panel (SOP) and three-dimensional (3D) ultrahigh density memories.…”