An on-chip low-loss and high conversion efficiency plasmonic waveguide converter is demonstrated at sub-THz in CMOS. By introducing a subwavelength periodic corrugated structure onto the transmission line (T-line) implemented by a top-layer metal, surface plasmon polaritons (SPP) are established to propagate signals with strongly localized surface-wave. To match both impedance and momentum of other on-chip components with TEM-wave propagation, a mode converter structure featured by a smooth bridge between the Ground coplanar waveguide (GCPW) with 50 Ω impedance and SPP T-line is proposed. To further reduce area, the converter is ultimately simplified to a gradual increment of groove with smooth gradient. The proposed SPP T-lines with the converter is designed and fabricated in the standard 65 nm CMOS process. Both near-field simulation and measurement results show excellent conversion efficiency from quasi-TEM to SPP modes in a broadband frequency range. The converter achieves wideband impedance matching (<−9 dB) with excellent transmission efficiency (averagely −1.9 dB) from 110 GHz–325 GHz. The demonstrated compact and wideband SPP T-lines with mode converter have shown great potentials to replace existing waveguides as future on-chip THz interconnects. To the best of the author’s knowledge, this is the first time to demonstrate the (sub)-THz surface mode conversion on-chip in CMOS technology.
By using 2 3 2 MIMO and photonics-aided heterodyne coherent detection based on advanced digital signal procession, we have experimentally demonstrated a radio-overfiber system which can reliably deliver a 59.52 Gbit/s PDM-SC-16QAM signal over a 20 km SMF-28 and a 40 m W-and wireless link with the BER less than HD-FEC threshold. When we extend the transmission fiber length to be 100 km, we can realize 51.2 Gbit/s PDM-SC-16QAM signal transmission over the same wireless link. To our knowledge, this is one record for the PDM-SC-16QAM signal wireless transmission at W-band.
AbstractIn this article, a novel two-stage 45-57 GHz low-power amplifier is presented and implemented in a 90-nm bulk CMOS technology. The crossing-capacitor neutralization technique is adopted to improve the gain and isolation of the amplifier. Meanwhile, the low-loss transmission line and on-chip transformer are designed for the matching networks. The measurement results show that the proposed amplifier achieves 3-dB gain bandwidth of 12 GHz, from 45 to 57 GHz. The maximum small-signal gain of this amplifier is 7.2 dB at 48.4 GHz, and the output 1-dB compression power is 26.8 dBm at 48.4 GHz. This amplifier consumes total power of 5.52 mW under 1.2 V voltage supply.
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A novel double-π equivalent circuit model for on-chip spiral inductors is presented. A hierarchical structure, similar to that of MOS models is introduced. This enables a strict partition of the geometry scaling in the global model and the model equations in the local model. The major parasitic effects, including the skin effect, the proximity effect, the inductive and capacitive loss in the substrate, and the distributed effect, are analytically calculated with geometric and process parameters in the local-level. As accurate values of the layout and process parameters are difficult to obtain, a set of model parameters is introduced to correct the errors caused by using these given inaccurate layout and process parameters at the local level. Scaling rules are defined to enable the formation of models that describe the behavior of the inductors of a variety of geometric dimensions. A series of asymmetric inductors with different geometries are fabricated on a standard 0.18-m SiGe BiCMOS process with 100 /cm substrate resistivity to verify the proposed model. Excellent agreement has been obtained between the measured results and the proposed model over a wide frequency range.
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