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To overcome limitations on bandwidth extension in conventional design techniques, a novel pole-converging technique with transformer feedback for intrastage bandwidth extension is proposed and analyzed in this paper. For verification, a three-stage cascode low-noise amplifier (LNA) based on the pole converging and negative drain-source transformer feedback is designed and implemented in a 65-nm CMOS technology. Consuming 27 mW dc power from a 1.8 V supply, the fabricated prototype exhibits peak power gain of 18.5 dB, minimum noise figure of 5.5 dB, 3-dB bandwidth of 30 GHz, and fractional bandwidth of 38.7%. The bandwidth of the three-stage cascode LNA is significantly extended without increasing power consumption and die size.

A fully integrated 93.4-104.8-GHz 57-mW fractional-N cascaded phase-locked loop (PLL) with true in-phase injection-coupled quadrature voltage-controlled oscillator (QVCO) is reported. By cascading the fractional-N PLL and the subsampling PLL, good phase noise, high resolution, and wide acquisition range are achieved simultaneously. The transformer-based true in-phase injection coupled technique is adopted in the QVCO to obtain both low phase noise and low-power consumption. The proposed cascaded PLL was fabricated in a 65-nm CMOS technology with silicon size of 0.88 mm 2 . The measured phase noise of QVCO and PLL is −113.26 and −106.63 dBc/Hz at 10-MHz offset, respectively. The FOM and FOM T of the QVCO at 10-MHz offset are −178.4 and −180.0 dBc/Hz, respectively. The frequency resolution of the 100-GHz output is less than 3.6 kHz.

A 65nm CMOS carrier-aggregation transceiver for IEEE 802.11 WLAN applications

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