A 65nm CMOS carrier-aggregation transceiver for IEEE 802.11 WLAN applications

Yi, Xiaoke; Yang, Kaituo; Liang, Zipeng; Liu, Bei; Khanna, Devrishi; Boon, Chirn Chye; Li, Chenyang; Feng, Guangyin; Regev, Dror; Shilo, Shimi; Meng, Fanman; Liu, Huan; Sun, Junyi; Hu, Gengen; Miao, Yanming

doi:10.1109/rfic.2016.7508252

Cited by 13 publications

(18 citation statements)

References 5 publications

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“…Voltage controlled oscillator (VCO) is an essential component in modern integrated circuit, such as radio-frequency (RF) transceivers [1,2,3,4,5,6,7,8] and clock data recovery (CDR) systems [9,10,11,12,13,14,15,16,17]. LC VCO has much better jitter performance but limit tuning range.…”

Section: Introductionmentioning

confidence: 99%

A low power wide tuning range two stage ring VCO with frequency enhancing

Yan¹,

Wu²,

Hu³

et al. 2019

IEICE Electron. Express

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A wide tuning range frequency enhanced two stage ring voltage controlled oscillator (VCO) is proposed in this letter. The proposed delay cell increases the transmission gain by inserting a resistor between input and output, which consumes lower power to generate same oscillating frequency. A rail-to-rail effective voltage tuning range is obtained by both tuning of tail current and the strength of cross coupled latch. It is important for advanced process, which has low standard supply voltage and high threshold voltage. The proposed VCO is fabricated in TSMC 40 nm CMOS technology. The measured phase noise of proposed VCO is −98.05 dBc/Hz at 1 MHz offset with 1.38 GHz carrier frequency while consuming 1.1 mW from a 1.1 V standard supply. The figure of merit (FoM) is 160.4 dBc/Hz.

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Section: Introductionmentioning

confidence: 99%

A low power wide tuning range two stage ring VCO with frequency enhancing

Yan¹,

Wu²,

Hu³

et al. 2019

IEICE Electron. Express

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“…application. This prototype includes three PLL frequency synthesizers and a buffer network for LO clock delivery [12]. In fact, CMOS PLL frequency synthesizers are commonly considered as the most complicated blocks in an RFIC, and usually determine the design cycle of a RFIC product [13].…”

Section: List Of Tablesmentioning

confidence: 99%

“…From a general point of view, the proposed techniques in this thesis aim to reduce noise from the error detectors. [11]- [12]). Crystal oscillators are still commonly used as the reference clock source for modern wireless transceiver PLLs.…”

Section: Parametersmentioning

confidence: 99%

“…where is an integer that ( + More generally, if there are phases to be selected, the output frequency would be = ( + ) , (3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16)(17)(18)(19)(20)(21) and the tuning step would be ∆ = . (3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16)(17)(18)(19)(20)(21)(22) This means that a finer tuning step can be achieved with more phases provided. The average shifted phase number during each is thus…”

Section: Constant-step Phase Switchingmentioning

confidence: 99%

“…As will be seen later, this is much lower than the contribution from phase noise of the oscillator. However, (4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15) does limit the signal bandwidth as the quantization noise increases dramatically with .…”

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confidence: 99%

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In-band phase noise reduction techniques for phase-locked loops in advanced CMOS technologies

Liang¹

Self Cite

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Phase-locked loops (PLLs) have been successfully used as frequency synthesizers for decades in complementary metal-oxide-semiconductor (CMOS) transceivers for wireless communications. However, modern developments in communications require PLLs with wider loop bandwidth and lower in-band phase noise. High in-band phase noise leads to serious consequences in communications, such as degraded signal-to-noise ratio (SNR) and constellation diagram, resulting in low communication quality. Therefore, low PLL in-band phase noise is crucial to the overall transceiver performance, especially in future high-speed high-quality wireless communications. Unfortunately, frequency synthesizers based on conventional PLL structures are facing challenges because their in-band phase noise is often limited by the phase detectors and charge pumps. Noises from these components are amplified due to the structure of the conventional PLLs. Furthermore, PLL often needs to achieve short settling time for some communication standards, and has to provide multi-phase output in some transceiver architectures. Inspired by these requirements, this thesis aims to enhance PLL in-band phase noise performance while meeting other important requirements of future wireless communications in the multi-GHz band.

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