In-band phase noise reduction techniques for phase-locked loops in advanced CMOS technologies

Abstract

Phase-locked loops (PLLs) have been successfully used as frequency synthesizers for decades in complementary metal-oxide-semiconductor (CMOS) transceivers for wireless communications. However, modern developments in communications require PLLs with wider loop bandwidth and lower in-band phase noise. High in-band phase noise leads to serious consequences in communications, such as degraded signal-to-noise ratio (SNR) and constellation diagram, resulting in low communication quality. Therefore, low PLL in-band phase noise is crucial to the overall transceiver performance, especially in future high-speed high-quality wireless communications. Unfortunately, frequency synthesizers based on conventional PLL structures are facing challenges because their in-band phase noise is often limited by the phase detectors and charge pumps. Noises from these components are amplified due to the structure of the conventional PLLs. Furthermore, PLL often needs to achieve short settling time for some communication standards, and has to provide multi-phase output in some transceiver architectures. Inspired by these requirements, this thesis aims to enhance PLL in-band phase noise performance while meeting other important requirements of future wireless communications in the multi-GHz band.