The development of concurrent dual-band wireless transceiver has enhanced the miniaturization of all blocks used in the wireless transceiver. That is achieved by casting the two single-band blocks into a dual-band block. In this paper, a dual-band BPF for the concurrent dual-band wireless transceiver is developed. A stepped impedance resonator (SIR) is used to implement the dual-band BPF because of its controllable spurious response property. The filter is implemented on the LTCC substrate, where the second pass-band is obtained by making use of the spurious response. Here, a 590x590 mils' dual-band BPF that has center frequencies of 2.4GHz and 5.2GHz, less than 2dB insertion loss, greater than 20dB return loss, and more than 5% handwidth is successfully developed.
IntroductionThe diverse range of modem wireless applications necessitates the communication systems with more bandwidth and flexibility. The standard heterodyne transceiver architecture accomplishes high selectivity and sensitivity by a narrow band operation. However, this mode of operation limits the system's available bandwidth, which can be translated to a limited number of available channels and functionality [2]. In the beginning, those problems are overcome by using wide-band mode of operation. Nevertheless, this solution leads to a more sensitive system due to noise and interference of the unwanted signals that are caused by the non-linearity of the system. Later, transceivers with two parallel systems working at two different frequencies are introduced to increase the communication system functionality. It is achieved by allowing simultaneous operation at different frequency bands. However, this technique results in increasing number of block used, which results in a system with higher cost,
This letter presents a D-band wideband power amplifier (PA) in a 65-nm CMOS process. By pole-tuning technique with T-type network, the PA achieves a flat gain response over a wide bandwidth. The high output power is achieved by combining the output power of two PA cells using a Y-type power combiner (YPC). The fabricated prototype achieves a peak gain of 11.5 dB at 115 GHz with a 3-dB bandwidth of more than 21 GHz and a fractional bandwidth of larger than 17.5%. At the operating frequency of 120 GHz, the saturation output power and the output P 1dB are 13 dBm and 8.7 dBm, respectively. The chip occupies a small silicon area of 0.59 mm 2 including all testing pads with a core size of only 0.32 mm 2 .
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