We demonstrate highly robust flexible a-IGZO thin-film transistors (TFTs) with imbedded carbon nano-tube (CNT) buried electrode (BE) in between polyimide (PI) substrate. The excellent mechanical durability of flexible TFTs on thin wrinkle-free and the self-standing PI substrate with imbedded CNT BE has been demonstrated. The strain on the TFT can be reduced by the imbedded CNT electrode which is calculated from the 3D-TCAD simulation.
KeywordsAmorphous-indium-gallium-zinc-oxide (a-IGZO), thin-film transistor (TFT), buried electrode (BE), Technology computeraided design (TCAD).
We present an accelerated SmartSpice model that can detect dynamic threshold voltage shift (ΔVth)‐related failure of an oxide thin‐film transistor (TFT)‐based gate driver. During gate driver operation, the alternating HIGH and LOW input signals repeatedly stress and relax the TFT components of the gate driver. Because oxide TFTs do not recover completely during the LOW input level, ΔVth cumulated during the HIGH input levels may result in failure of gate drivers. For correct failure analysis, a TFT model that can detect dynamic ΔVth is, therefore, needed to replace current TFT models, as they cannot account for dynamic ΔVth. The model presented herein works correctly with varying temperature and input signals of any shape.
The procedure to calibrate TCAD simulation data, based on both measurement data and the probability of occupation functions, is described . By using a density-of-states model and a band-to-band tunneling model in the Silvaco Atlas device simulator, insight into the TFTs and more accurate TCAD simulations can be obtained.
We analyzed that how gate-poly-undercuts caused the disturbance failure in static random access memory (SRAM) bit-cells embedded in display driver integrated circuit (DDI) products. The beta ratio (I ON of the pull-down transistor / I ON of the pass-gate transistor) degradation induced by gate-poly undercuts was the main factor of the disturbance failure. Regarding the relation of undercuts and beta ratio, the hypothesis is as following: When the undercuts exist, dopants implanted with the halo process reach below the channel area more closely and it makes well concentration more high. Hence, the performance of the transistor (TR) with undercut becomes slower than normal TR. As the gate length of the pull-down (PD) TR is smaller than that of the pass-gate (PS) TR, the performance of the PD TR becomes more degraded than that of the PS TR. Consequently, the beta ratio decreases. To enhance beta ratio, we changed the thickness of photo-mask materials for the gate-poly layer and reduced the gate-poly etch time. Thanks to those actions, beta ratio was improved and we could completely overcome the disturbance failure issue.
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