The development of Double-Patterning (DP) techniques continues to push forward aiming to extend the immersion based lithography below 36 nm half pitch. There are widespread efforts to make DP viable for further scaling of semiconductor devices. We have developed Develop/Etch/Develop/Etch (DE2) and Double-Expose-Track-Optimized (DETO) techniques for producing pitch-split patterns capable of supporting semiconductor devices for the 16 nm and 11 nm nodes. The IBM Alliance has established a DETO baseline, in collaboration with ASML, TEL, CNSE, and KLATencor, to evaluate the manufacturability of DETO by using commercially available resist systems. Presented in this paper are the long-term performance results of these systems relevant to defectivity, overlay, and CD uniformity.
At the 5 nm technology node there are competing strategies for patterning: high-NA EUV, double patterning 0.33 NA EUV and a combination of optical self-aligned solutions with EUV. This paper investigates the impact of pattern shift based on the selected patterning strategy. A logic standard cell connection between TS and M0 is simulated to determine the impact of lithographic pattern shift on the overlay budget. At 5 nm node dimensions, high-NA EUV is necessary to expose the most critical layers with a single lithography exposure. The impact of high-NA EUV lithography is illustrated by comparing the pattern shift resulting from 0.33 NA vs. 0.5x NA. For the example 5 nm transistor, cost-beneficial lithography layers are patterned with EUV and the other layers are patterned optically. Both EUV and optical lithography simulations are performed to determine the maximum net pattern shift. Here, lithographic pattern shift is quantified in terms of through-focus error as well as pattern-placement error. The overlay error associated with a hybrid optical/selfaligned and EUV cut patterning scheme is compared with the results of an all EUV solution, providing an assessment of two potential patterning solutions and their impact the overall overlay budget.
One method currently being employed to reduce the overall lithography process complexity and cost is the utilization of a topcoatless photoresist. The development of these materials administers an additive to create the same hydrophobic characteristics as those created by advanced topcoats. The main challenge for topcoatless resists is to increase the hydrophobicity without causing too much inhibition at the resist surface which leads to bridging or residue-type defects. The key to such a design lies in creating a balance between leaching control and dissolution characteristics of the resist without degrading lithography performance and increasing defectivity. The addition of these hydrophobic additives into existing ArF photoresist systems has been shown to increase both receding contact angle and advancing contact angle in water-based immersion lithography. In this work, the authors have demonstrated that the defectivity levels of topcoatless resist are equal to or better than the industry standard of topcoat systems. This was achieved by optimizing process conditions. This article will report the influences of the develop process, postcoat apply bake/ postexposure bake ͑PAB/PEB͒ temperatures, and immersion specific rinses on defect performance of topcoatless resists. It was found that pattern collapse defects along nonexposed regions for some topcoatless material can be drastically reduced by PAB/PEB temperature optimization. Complete elimination of missing pattern defects achieved by use of de-ionized water immersion specific rinses for all materials tested. Finally, the impact of the PAB temperature on surface properties will be investigated.
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