Evaluation of double-patterning techniques for advanced logic nodes

Optical lithography, currently being used for 45-nm semiconductor devices, is expected to be extended further towards the 32-nm and 22-nm node. A further increase of lens NA will not be possible but fortunately the shrink can be enabled with new resolution enhancement methods like source mask optimization (SMO) and double patterning techniques (DPT). These new applications lower the k1 dramatically and require very tight overlay control and CD control to be successful. In addition, overall cost per wafer needs to be lowered to make the production of semiconductor devices acceptable. For this ultimate era of optical lithography we have developed the next generation dual stage NXT:1950i immersion platform. This system delivers wafer throughput of 175 wafers per hour together with an overlay of 2.5nm. Several extensions are offered enabling 200 wafers per hour and improved imaging and on product overlay.The high productivity is achieved using a dual wafer stage with planar motor that enables a high acceleration and high scan speed. With the dual stage concept wafer metrology is performed in parallel with the wafer exposure. The free moving planar stage has reduced overhead during chuck exchange which also improves litho tool productivity.In general, overlay contributors are coming from the lithography system, the mask and the processing. Main contributors for the scanner system are thermal wafer and stage control, lens aberration control, stage positioning and alignment. The back-bone of the NXT:1950i enhanced overlay performance is the novel short beam fixed length encoder grid-plate positioning system. By eliminating the variable length interferometer system used in the previous generation scanners the sensitivity to thermal and flow disturbances are largely reduced. The alignment accuracy and the alignment sensitivity for process layers are improved with the SMASH alignment sensor. A high number of alignment marker pairs can be used without throughput loss, and furthermore the GridMapper functionality which is using the inter-die and intra-die scanner capability can reduce overlay errors coming from mask and process without productivity impact.In this paper we will present the main design features and discuss the system performance of the NXT:1950i system, focusing on the improvements made in overlay and productivity. We will show data on imaging, overlay, focus and productivity supporting the 3X-nm node and we will discuss next improvement steps towards the 2X-nm node.

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“…( ) Figure 17 Litho Freeze Litho overlay on resolution results and spaces CDU using a process as described in [2].…”

Section: Litho Freeze Lithomentioning

confidence: 99%

“…The second relevant application is a Litho Freeze Litho (LFL) application using a thermal cure process as described in [2] . The CDU of the spaces is determined by the overlay between the 2 exposures and the CDU of the lines following equation 1 [10] .…”

Section: Litho Freeze Lithomentioning

confidence: 99%

Towards ultimate optical lithography with NXT:1950i dual stage immersion platform

et al. 2010

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“…Over the past years, EUV lithography has been actively researched and developed as the next-generation lithography (NGL) solution although its readiness for high volume manufacturing (HVM) has been long-awaited and still unclear 1,2 . Double patterning techniques, such as litho-litho-etch (LLE) 3,4 , litho-etch-litho-etch (LELE) 5,6 , and self-aligned double patterning (SADP) 7,8 have been developed to extend the ultimate resolution k 1 factor of 193 nm immersion lithography. However, the need for device scaling in 14 nm and beyond technology nodes necessitates the implementation of more aggressive multiple patterning techniques 9,10 .…”

Section: Introductionmentioning

confidence: 99%

Novel and cost-effective multiple patterning technology by means of invisible SiO_xNy hardmask

et al. 2014

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The Cost of Ownership (CoO) for semiconductor processing has been primarily dominated by lithography. In multiple patterning processes, additional materials and the impact to throughput of multiple patterning passes appear to become additional major contributors to manufacturing cost as well. We introduce SiO x N y hardmask as a new memorization layer for multiple patterning that addresses the non-lithographic cost contributor to manufacturing. The optical constants of the SiO x N y hardmask are matched to those of the photoresist at the imaging wavelength, and that makes it invisible at the exposure wavelength, enabling lithography directly over the hardmask topography, while at the same time it will be visible to those wavelengths that are used for alignment and overlay. The SiO x N y hardmask is inserted below the photoresist which will make the rework and integration schemes much simpler and result in cost savings by replacing only photoresist layers during multiple patterning processes. Additionally, by eliminating the need for traditional spincast planarization and the associated tri-layer etch we can improve the critical dimension uniformity (CDU) and reduce proximity contributions from etch, and their respective etch proximity corrections. In this work, we engineered the lithographic stack to be compatible with the invisible SiO x N y hardmask. Lithographic process windows, CDU, and LER/LWR are compared with conventional tri-layer stack and we demonstrate triple patterning memorized into the SiO x N y hardmask after which patterns are then transferred, at once, into the bottom integrated stack. Finally, major benefits of using the invisible hardmask on device scaling and patterning challenges are discussed, such as for LE 2 , LE 3 , and trench and cut patterning.

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“…There have been many discussions [1][2][3][4][5] on wafer process and layout decomposition for two typical double patterning approaches: Litho-Etch-Litho-Etch (LELE) and Self-Aligned Double Patterning with spacer lithography (SADP). It has been shown that there are additional process constraints due to the double patterning nature of DPT.…”

Section: Introductionmentioning

confidence: 99%

DPT restricted design rules for advanced logic applications

Deng

Yoshida

et al. 2011

SPIE Proceedings

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Double patterning technology (DPT) provides the extension to immersion lithography before EUV lithography or other alternative lithography technologies are ready for manufacturing. Besides the additional cost due to DPT processes over traditional single patterning process, DPT design restrictions are of concerns for potential additional design costs. This paper analyzes design restrictions introduced by DPT in the form of DPT restricted design rules, which are the interface between design and technology. Both double patterning approaches, Litho-Etch-Litho-Etch (LELE) and Self-Aligned Double Patterning with spacer lithography (SADP), are studied. DPT design rules are summarized based on drawn design layers instead of decomposed layers. It is shown that designs can be made DPT compliant designs if DPT design rules are enforced and DPT coloring check finds no odd cycles. This paper also analyzes DPT design rules in the design rule optimization flow with examples. It is essential to consider DPT design rules in the integrated optimization flow. Only joint optimization in design rules between design, decomposition and process constraints can achieve the best scaled designs for manufacturing. This paper also discusses DPT enablement in the design flow where DPT aware design tools are needed so that final designs can meet all DPT restricted design rules.

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Evaluation of double-patterning techniques for advanced logic nodes

Cited by 8 publications

References 6 publications

Towards ultimate optical lithography with NXT:1950i dual stage immersion platform

Towards ultimate optical lithography with NXT:1950i dual stage immersion platform

Novel and cost-effective multiple patterning technology by means of invisible SiO_xNy hardmask

DPT restricted design rules for advanced logic applications

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Evaluation of double-patterning techniques for advanced logic nodes

Cited by 8 publications

References 6 publications

Towards ultimate optical lithography with NXT:1950i dual stage immersion platform

Towards ultimate optical lithography with NXT:1950i dual stage immersion platform

Novel and cost-effective multiple patterning technology by means of invisible SiOxNy hardmask

DPT restricted design rules for advanced logic applications

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Product

Resources

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Novel and cost-effective multiple patterning technology by means of invisible SiO_xNy hardmask