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A modified memory-space-memory (MSM) Closnetwork switch, called MCNS, with a module-level matching packet dispatching scheme, is presented in the paper. The MCNS is a modification of the MSM Clos-network switch proposed to simplify the packet dispatching scheme. In this paper, we evaluate the combinatorial properties of the MCNS, as well as a new module-level matching packet dispatching algorithm. We also show how this algorithm can be implemented in an field-programmable gate array chip. Selected simulation results obtained for the MCNS are compared with the results obtained for the MSM Clos-network switch using other module-level matching algorithms.

The CBC stands for the Central-stage Buffered Clos-network. This kind of switching fabric was proposed and theoretically evaluated by F. Wang and M. Hamdi. In this paper new packet dispatching schemes for the CBC switches are proposed and evaluated. We study three such schemes, called RGNA (Request -Grant with No Association), RGAM (RequestGrant with Associated output Modules), and RGAP (RequestGrant with Associated output Ports). Our research is aimed at finding an answer to the question: what kind of packet dispatching scheme should be used in the CBC switch to achieve very good performance in terms of throughput, cell delay and central buffers size. The uniform and nonuniform traffic distribution patterns are used to evaluate the performance of the CBC switch. Using computer simulation we try to fill an important gap between the theory and practical implementation of interesting switch architecture.

Rapid expansion of the Internet and increasing demand for multimedia services fosters an immediate need for the development of new high-capacity networks capable of supporting these growing bandwidth requirements. The development of broadband transport networks resulted in the need for next generation switches/routers with high-speed interfaces and large switching capacity. The main part of every switching node is a switching fabric, which provides a connecting path between input and output lines. For high-performance switches and routers the Clos-network is very attractive because of its modular architecture and scalability. In packet switching systems packet dispatching algorithms were adopted to avoid packet contention, which may occur while a packet is being routed in a switching fabric. Different dispatching schemes for the buffered Clos-network switches were proposed in many papers. Most of them consist of request, grant and accept phases, and cannot work in the real environment. In this paper the application of static connection patterns to packet dispatching algorithms for the three-stage buffered Clos-network switches is proposed. The performance of two such algorithms, called Static Desynchronization (SD) and Maximal Matching Static Desynchronization (MMSD), is evaluated and compared with results obtained for CRRD (Concurrent Round-Robin Dispatching) and CMSD (Concurrent Master-Slave Round-Robin Dispatching) schemes. We would like to show that it is possible to use a very simple packet dispatching scheme and obtain an acceptable performance for a wide range of traffic load per input port.

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