CRRD-OG: a packet dispatching algorithm with open grants for three-stage buffered clos-network switches

Kleban, Janusz; Wieczorek, Andrzej

doi:10.1109/hpsr.2006.1709727

Cited by 14 publications

(14 citation statements)

References 13 publications

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“…Two scheduling phases are required to resolve input-output ports contention. In addition to its high cost and long scheduling delays, no scheduling algorithm for this architecture has been shown to exhibit satisfactory performance [8] [11]. MMM [7] [2] mandate large and expensive internal memories to relax the scheduling process.…”

Section: Related Workmentioning

confidence: 99%

“…The need for a conflict-free matching in conventional Closnetwork switches, such as MSM, mandates the need of two types of matchings [8] [10] [11]: a matching within each input module to select eligible VOQs among non-empty candidate VOQs and a second matching between IMs and CMs. Both of these matchings are quite complex and time consuming due to the high number of input queues per IM for the first matching as well as the global synchronisation of input-output port pairs for IM-CM matching to produce a conflict-free match.…”

Section: Im Matching and CM Dispatchingmentioning

confidence: 99%

“…The scheduling (or dispatching) process in current multistage Clos networks, especially the MSM type, is very complex and expensive, yet has poor performance under non-uniform traffic scenarios. A typical example of this is the Concurrent Round Robin Dispatching (CRRD) for MSM and its enhanced versions [10] [11].…”

Section: Introductionmentioning

confidence: 99%

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A Multi-Stage Packet-Switch Based on NoC Fabrics for Data Center Networks

Hassen

Mhamdi

2015

2015 IEEE Globecom Workshops (GC Wkshps)

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Abstract-Bandwidth-hungry applications such as Cloud computing, video sharing and social networking drive the creation of more powerful Data Centers (DCs) to manage the large amount of packetized traffic. Data center network (DCN) topologies rely on thousands of servers that exchange data via the switching backbone. Cluster switches and routers are employed to provide interconnectivity between elements of the same DC and inter DCs and must be able to handle the continuously variable loads. Hence, robust and scalable switching modules are needed. Conventional DCN switches adopt crossbars or/and blocks of memories in multistage interconnection architectures (commonly 2-Tiers or 3-Tiers). However, current multistage packet switch architectures, with their space-memory variants, are either too complex to implement, have poor performance, or not cost effective. In this paper, we propose a novel and highly scalable multistage packet-switch design based on Networks-on-Chip (NoC) fabrics for DCNs. In particular, we describe a novel three-stage packet-switch fabric with a Round-Robin packets dispatching scheme where each central stage module is based on a Unidirectional NoC (UDN), instead of a conventional singlehop crossbar fabric. The proposed design, referred to as Clos-UDN, overcomes all the shortcomings of conventional multistage architectures. In particular, as we shall demonstrate, the proposed Clos-UDN architecture: (i) Obviates the need for a complex and costly input modules, by means of few, yet simple, input FIFO queues. (ii) Avoids the need for a complex and synchronized scheduling process over a high number of input-output modules and/or port pairs. (iii) Provides speedup, load balancing and path-diversity thanks to a dynamic dispatching scheme as well as the NoC based fabric nature. Extensive simulation studies are conducted to compare the proposed Clos-UDN switch to conventional multistage switches. Simulation results show that the Clos-UDN outperforms conventional design under a wide range of input traffic scenarios, making it highly appealing for ultra-high capacity DC networks.

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Section: Related Workmentioning

confidence: 99%

Section: Im Matching and CM Dispatchingmentioning

confidence: 99%

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A Multi-Stage Packet-Switch Based on NoC Fabrics for Data Center Networks

Hassen

Mhamdi

2015

2015 IEEE Globecom Workshops (GC Wkshps)

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“…Second, the speed of the router for optical networking applications become limited by the advances in DRAM technologies whose access time has been reducing only at 7% per year [15]. Third, the limitations in electronic switch capacity [16][17][18] [14].…”

Section: Photonic Buffers In Optical Packet Switches and Routersmentioning

confidence: 99%

Photonic Data Buffers

Yoo

2015

Photonics

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“…In this architecture, the memory speed remains compatible with the line rate, but a good matching algorithm between inputs and outputs is needed, so that it can achieve high throughput and low latency. Different scheduling algorithms for VOQ switches were considered in the literature, most of them achieve 100% throughput under the uniform traffic, but the throughput is usually reduced under the non-uniform traffic [1,[4][5][6][7][8][9][10][11]14].…”

Section: Introductionmentioning

confidence: 99%

Packet Dispatching Algorithms with the Static Connection Patterns Scheme for Three-Stage Buffered Clos-Network Switches

Kleban

Santos²

2007

2007 IEEE International Conference on Communications

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Rapid expansion of the Internet and increasing demand for multimedia services fosters an immediate need for the development of new high-capacity networks capable of supporting these growing bandwidth requirements. The development of broadband transport networks resulted in the need for next generation switches/routers with high-speed interfaces and large switching capacity. The main part of every switching node is a switching fabric, which provides a connecting path between input and output lines. For high-performance switches and routers the Clos-network is very attractive because of its modular architecture and scalability. In packet switching systems packet dispatching algorithms were adopted to avoid packet contention, which may occur while a packet is being routed in a switching fabric. Different dispatching schemes for the buffered Clos-network switches were proposed in many papers. Most of them consist of request, grant and accept phases, and cannot work in the real environment. In this paper the application of static connection patterns to packet dispatching algorithms for the three-stage buffered Clos-network switches is proposed. The performance of two such algorithms, called Static Desynchronization (SD) and Maximal Matching Static Desynchronization (MMSD), is evaluated and compared with results obtained for CRRD (Concurrent Round-Robin Dispatching) and CMSD (Concurrent Master-Slave Round-Robin Dispatching) schemes. We would like to show that it is possible to use a very simple packet dispatching scheme and obtain an acceptable performance for a wide range of traffic load per input port.

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CRRD-OG: a packet dispatching algorithm with open grants for three-stage buffered clos-network switches

Cited by 14 publications

References 13 publications

A Multi-Stage Packet-Switch Based on NoC Fabrics for Data Center Networks

A Multi-Stage Packet-Switch Based on NoC Fabrics for Data Center Networks

Photonic Data Buffers

Packet Dispatching Algorithms with the Static Connection Patterns Scheme for Three-Stage Buffered Clos-Network Switches

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