Performance Evaluation of Selected Packet Dispatching Schemes for the CBC Switches

Abstract

The CBC stands for the Central-stage Buffered Clos-network. This kind of switching fabric was proposed and theoretically evaluated by F. Wang and M. Hamdi. In this paper new packet dispatching schemes for the CBC switches are proposed and evaluated. We study three such schemes, called RGNA (Request -Grant with No Association), RGAM (RequestGrant with Associated output Modules), and RGAP (RequestGrant with Associated output Ports). Our research is aimed at finding an answer to the question: what kind of packet dispatching scheme should be used in the CBC switch to achieve very good performance in terms of throughput, cell delay and central buffers size. The uniform and nonuniform traffic distribution patterns are used to evaluate the performance of the CBC switch. Using computer simulation we try to fill an important gap between the theory and practical implementation of interesting switch architecture.

Multiservice Switching Networks with Overflow Links and Resource Reservation

“…Switching networks are the most important element of network nodes and significantly influence the effectiveness of telecommunication networks. Switching networks can be divided into nonblocking and blocking networks [1][2][3][4][5][6][7]. In nonblocking networks, the phenomenon of internal blocking, manifested by the lack of any possibility of setting up a connection between a free input and a free output, is nonexistent [8].…”

Internal Backpressure for Terabit Switch Fabrics

“…Depending in which stage the memory is allocated, different architectures are possible, e.g., Space-Memory-Space, Memory-SpaceMemory [9], Memory-Memory-Memory, Space-MemoryMemory (SMM) [8] (adopted in this work). For the first architecture to be practical advanced schedulers are required [10], whereas the second architecture requires complex dispatching schemes [9]. The Memory-Memory-Memory is considered the best performing Clos architecture, achieving 100% throughput, but it has been suggested recently that the memory in the first stage is not necessary [8].…”