No abstract

No abstract

No abstract

Stress Induced Leakage Current (SILC) has been obdown (HBD). NMOS Positive Bias Temperature Instability served on non-optimized high-K (HK) and metal-gate (MG) tran-(PBTI) degradation is a good indicator of trap creation in the sistors. Large NMOS PBTI degradation and correlation to SILC bulk-HK and can be correlated with SILC increase in NMOS. increase on such gate stack is a result of large trap generations inSILC has been also observed in SiO as well as SiN and is not the bulk-HK. This poses a long term reliability concern on prod-2 unique to HK dielectric [7]. Large SILC increase poses a threat uct standby power and can limit the operating voltage if not supto standby power increase on products if not suppressed as the pressed. On an optimized HK+MG process, we demonstrate that SILC has been suppressed. The transistor level SILC data, model gate leakage component increases substantially. Therefore, it is and Product burn-in stress data support this. With optimized critical that this mechanism must be thoroughly studied and process, SILC has no impact on products made of 45nm HK+MG suppressed in transistors made of HK dielectrics.transistors.

No abstract