Characterization of SILC and its end-of-life reliability assessment on 45NM high-K and metal-gate technology

Abstract

Stress Induced Leakage Current (SILC) has been obdown (HBD). NMOS Positive Bias Temperature Instability served on non-optimized high-K (HK) and metal-gate (MG) tran-(PBTI) degradation is a good indicator of trap creation in the sistors. Large NMOS PBTI degradation and correlation to SILC bulk-HK and can be correlated with SILC increase in NMOS. increase on such gate stack is a result of large trap generations inSILC has been also observed in SiO as well as SiN and is not the bulk-HK. This poses a long term reliability concern on prod-2 unique to HK dielectric [7]. Large SILC increase poses a threat uct standby power and can limit the operating voltage if not supto standby power increase on products if not suppressed as the pressed. On an optimized HK+MG process, we demonstrate that SILC has been suppressed. The transistor level SILC data, model gate leakage component increases substantially. Therefore, it is and Product burn-in stress data support this. With optimized critical that this mechanism must be thoroughly studied and process, SILC has no impact on products made of 45nm HK+MG suppressed in transistors made of HK dielectrics.transistors.

Detection of surface electronic defect states in low and high-k dielectrics using reflection electron energy loss spectroscopy

“…5,6 Although the implementation of both low and high-k dielectric materials by the industry has enabled impressive gains in device performance and the continuation of Moore's law, 7,8 the electrical properties of these low and high-k materials are reduced relative to SiO 2 , and there are significant electrical reliability concerns [9][10][11] as the industry seeks to continue to implement these materials in future ,15 nm and beyond technologies. 12,13 Specific electrical reliability concerns for low-and high-k dielectrics include line-line interconnect 14,15 and gate dielectric leakage, 16,17 dielectric breakdown (V bd ), [18][19][20] time-dependent dielectric breakdown, [21][22][23][24] stress-induced leakage currents, 25,26 bias temperature instabilities, 27,28 charge trapping, [29][30][31][32] and a host of other charge-related buildup phenomena. 33,34 Despite the wide range of reliability concerns, a key ingredient in the models for all of these phenomena is some type of "defect" or "trap" in the dielectric material.…”

Investigation of dependence between time-zero and time-dependent variability in high-κ NMOS transistors

“…The actual reason behind the SILC is a controversial issue. While some groups attribute the SILC phenomenon to the defect generation in the HK layers [30,34,35], others explain SILC by defect generation only in the IL layer [27,36]. J. Yang, et al [13] argued that SILC is caused by defects in both HK and IL layers but mostly dominated by the defects in the IL layer since they have much lower relaxation energy.…”