Abstract-Discrete microprocessor-based equipment is a typical synchronization system on the market which implements the most critical features of the synchronization protocols in hardware and the synchronization algorithms in software. In this paper, a new clock discipline algorithm for hardware implementation is presented, allowing for full hardware implementation of synchronization systems. Measurements on field-programmable gate array prototypes show a fast convergence time (below 10 s) and a high accuracy (1 µs) for typical configuration parameters.
This contribution presents the design and implementation of a SNTP client module suitable for IEC 61850 environments fully done in hardware. The module is able to provide synchronization and accurate time reference within a microsecond with respect to a SNTP server, in a extremely compact, cost-effective and low power device completely implemented in a low grade FPGA chip. Therefore it can be an ideal replacement to expensive computer-based solutions or dedicated GPS receivers in a wide range of industrial applications. This SNTP client is part of a common technological platform for implementing Remote Terminal Units (RTUs) under IEC 61850.
Many people may see the development of software and hardware like different disciplines. However, there are great similarities between them that have been shown due to the appearance of extensions for general purpose programming languages for its use as hardware description languages. In this contribution, the approach proposed by the MyHDL package to use Python as an HDL is analyzed by making a comparative study. This study is based on the independent application of Verilog and Python based flows to the development of a real peripheral. The use of MyHDL has revealed to be a powerful and promising tool, not only because of the surprising results, but also because it opens new horizons towards the development of new techniques for modeling and verification, using the full power of one of the most versatile programming languages nowadays.
a b s t r a c tTraditional on-chip and off-chip logic analyzers present important shortcomings when used for the longterm verification of industrial embedded systems, forcing the designer to implement ad hoc verification solutions. This paper introduces a suitable solution for long-term verification of FPGA-based designs consisting of a verification core that uses the PicoBlaze microcontroller, dedicated logic and a serial port communication in order to monitor the internal signals of the system in a continuous way. The core design focuses on low resource requirements and has been successfully applied to the verification of a real industrial synchronization platform showing remarkable advantages over commercial on-chip solutions like Xilinx's ChipScope Pro. Moreover, in order to improve the reusability of this core a software tool has been developed to automatically include the verification core in any specific system.
This paper introduces a design and on-chip verification framework for IPCores in FPGA platforms. The methodology of the proposed framework is based on the development of a high level software model, an HDL description of the IPCore and the verification of the system under test by the Autotest Core, an onchip verification core developed for this framework. The test pattern generation is done at the high level in software and used throughout the design and verification process. HDL simulation results can then be compared to on-chip results and get performance measurements from the Autotest Core. The Off-line testing is possible by using standard low-cost Flash storage (SD card). The proposed framework and methodology applied to PRESENT and SPONGENT cryptographic algorithms has shown over two orders of magnitude better performance than commercial tools like Xilinx's VIO and a hardware footprint of the verification cored below 3% of the available FPGA resources.
This contribution successfully accomplished the design and implementation of an advanced DSP circuit for direct measurements of electrical network parameters (RMS and real and reactive power) with application to network monitoring and quality assurance.The device is implemented on a mid-range Xilinx Spartan-3 family FPGA and includes an OPB interface so that it can be integrated as a standardperipheral ofa microprocessor system like the MicroBlaze. Special attention has been paid to resources optimization and accuracy with simulated error below l%.
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