The rapid movement toward ultra-large-scale integration (ULSI) is significantly increasing the demands on testing technology for digital devices. Evolving test methodologies mustbe well integrated into the overall product realization process -from initial concept, through design, to field support. To maintain ever-increasing quality standards, high-quality tests mustidentify defective units at eachlevel ofsystem hierarchy. In addition, they must isolate faults to allow for efficient replacement and repair. Future demands on testing technology can be divided into sixmajor areas: product quality, device technology, testability scope, process integration, efficiency, and automation.
Three ASIC devices, recently designed at AT&T, incorporate the ANSI/IEEE Std 1149.1-1990 testability features. The test port is used for control of on-chip boundary-scan (BS) and full chip (macrocell and random logic) Built-In-Self-Test (BIST). Presented here will be a view of the methods used for implementation, novel circuit sharing between BIST and BS, and results related to device area, performance, fault coverage and testing.
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