Application of boundary-scan and full-chip BIST to a 3 ASIC chip set

Abstract

Three ASIC devices, recently designed at AT&T, incorporate the ANSI/IEEE Std 1149.1-1990 testability features. The test port is used for control of on-chip boundary-scan (BS) and full chip (macrocell and random logic) Built-In-Self-Test (BIST). Presented here will be a view of the methods used for implementation, novel circuit sharing between BIST and BS, and results related to device area, performance, fault coverage and testing.