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Hot-carrier degradation is associated with the buildup of defects at or near the silicon/silicon dioxide interfaced of a metal-oxide-semiconductor transistor. However, the exact location of the defects, as well as their temporal buildup during stress, is rarely studied. In this work we directly compare the experimental interface state density profiles generated during hot-carrier stress with simulation results obtained by a hot-carrier degradation model. The developed model tries to capture the physical picture behind hot-carrier degradation in as much detail as feasible. The simulation framework includes a transport module, a module describing the microscopic mechanisms of defect generation, and a module responsible for the simulation of degraded devices. Due to the model complexity it is very important to perform a thorough check of the output data of each module before it is used as the input for the next module. In this context a comparison of the experimental interface state concentration observed by the charge-pumping technique with the simulated one is of great importance. Obtained results not only show a good agreement between experiment and theory but also allow us to draw some important conclusions. First, we demonstrate that the multiple-particle mechanism of Si–H bond breakage plays a significant role even in the case of a high-voltage device. Second, the absence of the lateral shift of the charge-pumping signal means that no bulk oxide charge buildup occurs. Finally, the peak of interface state density corresponds to the peak of the carrier acceleration integral and is markedly shifted from typical markers such as the maximum of the electric field or the carrier temperature. This is because the degradation is controlled by the carrier distribution function and simplified schemes of hot-carrier treatment (based on the mentioned quantities) fail to describe the matter.

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We perform a comparative study of various macroscopic transport models against multisubband Monte Carlo (MC) device simulations for decananometer MOSFETs in an ultrathin body double-gate realization. The transport parameters of the macroscopic models are taken from homogeneous subband MC simulations, thereby implicitly taking surface roughness and quantization effects into account. Our results demonstrate that the drift-diffusion (DD) model predicts accurate drain currents down to channel lengths of about 40 nm but fails to predict the transit frequency below 80 nm. The energy-transport (ET) model, on the other hand, gives good drain currents and transit frequencies down to 80 nm, whereas below 80 nm, the error rapidly increases. The six moments model follows the results of MC simulations down to 30 nm and outperforms the DD and the ET models

Using a physics-based model for hot-carrier degradation we analyze the worst-case conditions for long-channel transistors of two types: a relatively low voltage n-MOSFET and a highvoltage p-LDMOS. The key issue in the hot-carrier degradation model is the information about the carrier energetical distribution function which allows us to asses the carrier acceleration integral determining the interface state build-up and which controls the interplay between the single-and multiple-carrier mechanisms of Si-H bond rupture. To analyze the worst-case conditions we generate intensity maps, i.e. dependences of some crucial quantities on source-drain Vds and gate Vgs stress voltage. These quantities are the boundary of the high-energy tail of the energy distribution function, the interface state generation rate and the total dose of degradation. The difference between positions of severest degradation spots evaluated according different criteria is also plotted as a function of stress voltages. Using these maps we demonstrate that the worst-case conditions are realized at 0.4Vds < Vgs < 0.5Vds for the n-MOSFET and at the maximal gate current for p-LDMOS. These findings correspond to experimental results published in the literature.

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The characteristics of modern semiconductor devices are strongly influenced by quantum mechanical effects. Due to this fact, purely classical device simulation is not sufficient to accurately reproduce the device behavior. For instance, the classical semiconductor equations have to be adapted to account for the quantum mechanical decrease of the carrier concentration near the gate oxide. Several available quantum correction models are derived for devices with one single inversion layer and are therefore only of limited use for thin double gate (DG) MOSFETs where the two inversion layers interact. We present a highly accurate quantum correction model which is even valid for extremely scaled DG MOSFET devices. Our quantum correction model is physically based on the bound states that form in the Si film. The eigenenergies and expansion coefficients of the wave functions are tabulated for arbitrary parabolic approximations of the potential in the quantum well. Highly efficient simulation of DG MOSFET devices scaled in the decananometer regime in TCAD applications is made possible by this model.