Hot-carrier degradation caused interface state profile—Simulation versus experiment

Abstract

Hot-carrier degradation is associated with the buildup of defects at or near the silicon/silicon dioxide interfaced of a metal-oxide-semiconductor transistor. However, the exact location of the defects, as well as their temporal buildup during stress, is rarely studied. In this work we directly compare the experimental interface state density profiles generated during hot-carrier stress with simulation results obtained by a hot-carrier degradation model. The developed model tries to capture the physical picture behind hot-carrier degradation in as much detail as feasible. The simulation framework includes a transport module, a module describing the microscopic mechanisms of defect generation, and a module responsible for the simulation of degraded devices. Due to the model complexity it is very important to perform a thorough check of the output data of each module before it is used as the input for the next module. In this context a comparison of the experimental interface state concentration observed by the charge-pumping technique with the simulated one is of great importance. Obtained results not only show a good agreement between experiment and theory but also allow us to draw some important conclusions. First, we demonstrate that the multiple-particle mechanism of Si–H bond breakage plays a significant role even in the case of a high-voltage device. Second, the absence of the lateral shift of the charge-pumping signal means that no bulk oxide charge buildup occurs. Finally, the peak of interface state density corresponds to the peak of the carrier acceleration integral and is markedly shifted from typical markers such as the maximum of the electric field or the carrier temperature. This is because the degradation is controlled by the carrier distribution function and simplified schemes of hot-carrier treatment (based on the mentioned quantities) fail to describe the matter.

Microscopic scale characterization and modeling of transistor degradation under HC stress

“…(5) and (6) (rigorous integral approach), with the one calculated with Eqs. (14) and (6) (E domi approach), we found similar results, as illustrated in Figs. 11 and 12.…”

“…While the Vg = Vd = 4.3 V stress condition has an EES contribution one order of magnitude lower than the non-EES part of the SP process, which may have a significant impact on the macroscopic degradation. Even if the EES contribution may be neglected in some cases, it should always be considered before adding other degradation phenomena into the channel, as it was proposed in [14,23].…”

“…Furthermore, depending on the stress condition, the degraded region along the channel length can also greatly vary [12][13][14]. As a consequence, it is necessary to monitor the degradation along the channel length and to model the generation of defect under HC stress, in order to improve our understanding of the HC degradation.…”

“…In our case, both degradation processes were fitted on stress conditions where they dominate the degradation, and verified on a large range of stress conditions. In other works [14,23], only high energy stress conditions were considered, with Vg < Vd. With measurement having a dominant SP process only, one cannot be sure of the parameters of the MP process.…”

“…Single Particle -induced interface state density along the channel length, calculated after E domi [3] Eqs. (14) and (6) and after the full integration of the DF Eqs. Fig.…”