Analysis of worst-case hot-carrier conditions for high voltage transistors based on full-band monte-carlo simulations

Starkov, Ivan A.; Tyaginov, Stanislav; Triebl, O.; Cervenka, J.; Jungemann, C.; Carniello, S.; Park, J.M.; Enichlmair, H.; Karner, M.; Kernstock, Ch.; Seebacher, E.; Minixhofer, R.; Ceric, H.

doi:10.1109/ipfa.2010.5532230

Cited by 5 publications

(6 citation statements)

References 24 publications

(46 reference statements)

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“…stressed at all combinations of V ds and V gs . This result agrees with our previous finding 10,19,29) as well as with the results published by the Bravaix group, 38) where it was demonstrated that the MVE-mechanism can provide a substantial contribution even if a gate length as long as 2.0 µm. As for the ABprocess, this mechanism provides the dominant contribution to hot-carrier degradation.…”

Section: Resultssupporting

confidence: 94%

On the Importance of Electron-electron Scattering for Hot-carrier Degradation

Tyaginov

Bina

Franco³

et al. 2014

Extended Abstracts of the 2014 International Conference on Solid State Devices and Materials

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Using our physics based model for hot-carrier degradation (HCD) we analyze the importance of the effect of electron-electron scattering (EES) on HCD in transistors with different channel lengths. The model is based on a thorough treatment of carrier transport and is implemented into the deterministic Boltzmann transport equation solver ViennaSHE. Two competing mechanism of Si-H bond-breakage are captured by the model: the one triggered by the multiple vibrational excitation of the bond and another which is due to excitation of one of the bonding electrons to an antibonding state by a solitary hot carrier. These processes are considered self-consistently as competing pathways of the same dissociation reaction. To analyze the importance of the EES process we use a series of nMOSFETs with identical architecture but different gate lengths. The gate length varies in the wide range of 44-300 nm to cover short-channel MOSFETs as well as their longer counterparts. According to previous findings, EES starts to become important at a channel length of 180 nm. This situation is captured in the targeted gate length interval. Our results show that the channel length alone is not a sufficient criterion on the importance of EES and that the applied bias conditions have to be taken into account as well.

show abstract

Section: Resultssupporting

confidence: 94%

On the Importance of Electron-electron Scattering for Hot-carrier Degradation

Tyaginov

Bina

Franco³

et al. 2014

Extended Abstracts of the 2014 International Conference on Solid State Devices and Materials

Self Cite

View full text Add to dashboard Cite

show abstract

“…stressed at all combinations of V ds and V gs . This result agrees with our previous finding 10, 19,29) as well as with the results published by the Bravaix group, 38) where it was demonstrated that the MVE-mechanism can provide a substantial contribution even if a gate length as long as 2.0 µm. As for the ABprocess, this mechanism provides the dominant contribution to hot-carrier degradation.…”

Section: (Color Online)supporting

confidence: 94%

“…Thus, in the previous version of our model the resulting interface state density was calculated as a superposition of AB-and MVE-induced contributions weighted with some probability coefficients. 10,19,[29][30][31] In the most recent version of our model, however, the AB-and MVEmechanisms are implemented self-consistently as competing pathways of the same reaction which converts pristine Si-H bonds into electrically active dangling Si bonds. We have already discussed that due to bond pre-heating by the MVEprocess the potential barrier for hydrogen release is reduced when the bond is in an excited state.…”

Section: Modeling Frameworkmentioning

confidence: 99%

On the importance of electron–electron scattering for hot-carrier degradation

Tyaginov

Bina

Franco

et al. 2015

Jpn. J. Appl. Phys.

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Using our physics based model for hot-carrier degradation (HCD) we analyze the importance of the effect of electron–electron scattering (EES) on HCD in transistors with different channel lengths. The model is based on a thorough treatment of carrier transport and is implemented into the deterministic Boltzmann transport equation solver ViennaSHE. Two competing mechanism of Si–H bond-breakage are captured by the model: the one triggered by the multiple vibrational excitation of the bond and another which is due to excitation of one of the bonding electrons to an antibonding state by a solitary hot carrier. These processes are considered self-consistently as competing pathways of the same dissociation reaction. To analyze the importance of the EES process we use a series of nMOSFETs with identical architecture but different gate lengths. The gate length varies in the wide range of 44–300 nm to cover short-channel MOSFETs as well as their longer counterparts. According to previous findings, EES starts to become important at a channel length of 180 nm. This situation is captured in the targeted gate length interval. Our results show that the channel length alone is not a sufficient criterion on the importance of EES and that the applied bias conditions have to be taken into account as well.

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“…In [47], the authors used full-band Monte Carlo simulations to analyze the worst-case conditions for high voltage transistors, while in [48], a method based on polynomial chaos theory was proposed to estimate the possible worst case of a measurement, due to the propagation of parametric uncertainty of a low-pass filter and a loop impedance. The extreme-value-analysis methods are also well studied, such as, the application of the genetic algorithms [49]- [51], interval analysis [52]- [54], and affine arithmetic [50] for worst-case circuit analysis.…”

Section: Goal Of the Thesismentioning

confidence: 99%

Worst-Case analysis of electrical and electronic equipment via affine arithmetic

Ding

Zhang

Trinchero

et al. 2017

2017 International Conference on Electromagnetics in Advanced Applications (ICEAA)

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I would like to thank several people who have contributed in different ways towards the work accomplished in this thesis. First and foremost, I would like to express my utmost gratitude to my supervisor, Prof. Flavio Canavero, for his encouragement, guidance, and support. His wide knowledge and insightful comments have made my candidature a truly enriching experience. I would also like to express my sincerest appreciation to my co-supervisor, Prof. Igor Stievano. His patience, motivation, and guidance have benefitted me immensely. This thesis work would not have been possible without his insightful thoughts. I would thank Dr. Paolo Manfredi and Riccardo Trinchero, for their time and efforts devoted in my research work, for the valuable suggestions and critical questions during this thesis. I also acknowledge my colleagues, Marchisio, Petrini, Fontana, Figura, Ubolli and Elisabetta, for their help and accompany in the last three years. Thanks to Dr. Sun Wen and Dr. Jiang Yanchao, for their generous help and encouragement. Finally, thanks to my best friends, Tiegang, Cunfa and Yuekun who have always been so supportive. And many thanks to my family, to my parents for their constant support in my life. To them I dedicate this thesis.

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Analysis of worst-case hot-carrier conditions for high voltage transistors based on full-band monte-carlo simulations

Cited by 5 publications

References 24 publications

On the Importance of Electron-electron Scattering for Hot-carrier Degradation

On the Importance of Electron-electron Scattering for Hot-carrier Degradation

On the importance of electron–electron scattering for hot-carrier degradation

Worst-Case analysis of electrical and electronic equipment via affine arithmetic

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