IntroductionA high performance 0.20pm logic technology has been developed with six levels of planarized copper interconnects. 0.15pm transistors (Lg,,,=0.15+0.04pm) are optimized for 1.8V operation to provide high performance with low power-delay products and excellent reliability. Copper has been integrated into the back-end to provide low resistance interconnects. Critical layer pitches for the technology are summarized in Table 1 and enable fabrication of 7.6pm2 6T SRAM cells.Isolation and Transistors CMP planarized shallow trenches with good electrical isolation down to n+/p+ spacings of 0.5pm were fabricated (Fig. 1). Dual gate 0.15pm transistors with 35A physical gate oxides (accumulation t,,=39A measured at Vg=+l .SV) were formed using super steep retrograde channels, shallow extensions and halos, relatively deep source/drain regions and 1 OOnm nitride spacers. CoSi, was selectively formed on the polysilicon gates and source/drain regions with a nominal sheet resistance of 9Wsq. Rapid thermal processing was utilized as much as possible throughout the flow to minimize transient enhanced dopant diffusion.Fig. 2 shows a typical SEM cross-section of a NMOS transistor with a gate length of 0.15pm. Well delineated shallow S/D extensions and the deeper S/D junctions are clearly observed. The saturation drive currents for nominal gate length NMOS and PMOS devices are shown in Fig. 3 . The nominal drive currents are 630pNpm for NMOS and 230pA/ym for PMOS at 1.8V. The off-state leakage currents of these devices are well below the worst case leakage specification of 2nA/pm. The drain induced barrier lowering (DIBL) measured on NMOS and PMOS devices is plotted as a function of Leff in Fig. 4. Good short channel characteristics are maintained down to effective channel lengths of O.1ym. The Vt roll-off for N and P devices in the linear and saturation regions are shown in Fig. 5. The Vt's are 0.44V and -0.46V for Nch and Pch respectively, at a gate length of 0.15pm and the associated subthreshold slopes are less than 90mv/dec. The use of nitrided gate oxides was investigated due to their superior hot carrier reliability. Fig. 6 compares the degradation under hot carrier stress of nitrided oxides to thermal oxides and highlights the improved reliability of NO-annealed oxides. Peak Gms comparable to those from thermal oxides were obtained (Fig. 7). A further advantage afforded by nitrided gate dielectrics is its superior boron blocking properties, Increasing the poly silicon doping in the P+ gate to reduce poly depletion resulted in only a 88mV Vt shift in nitrided oxides (Fig. 8) compared to a 300mV Vt shift in thermal oxides. A significant reduction in the inversion to, is achieved with the higher gate doping, resulting in improved device characteristics. NMOS transistor design focused on minimizing defect enhanced dopant re-distribution such as TED. To this end, the effect of different source/drain implant energies on NMOS transistor performance is shown in Fig. 9. The lower energy implant results in a significantl...
O 9 (SBBT) thin films prepared by the metal-organic decomposition method on Pt/Ti/SiO 2 /Si substrates have been investigated. It was observed that the microstructure and electrical properties of SBBT thin films dramatically varied with the Ba content. While the remanent polarization and dielectric constant decreased with increasing Ba content in SBBT thin films, the insulating properties significantly improved. The SBBT films also exhibited good fatigue characteristics under bipolar stressing to 10 10 cycles.
We have developed the single ferroelectric field-effect-transistor technology using a ferroelectric SBT(SrBi2Ta209) and NO(Si3N4/Si02) materials which were compatible with the standard Si CMOS process. The SBT/NO combined layer was used as a gate dielectric layer of MFISFET device. A small-sized MFlSFET having 10/3pmwidth/length of gate was fabdcated. The memory window of n-channel and p-channel MFISFET are all about 2.0 V. The threshold voltages of n-channel and p-channel MFISFET are about 1.8V and -2.1 V. The current difference between the IoN(on current) and IOw(off current) for sensing margin is more than I 0 0 times in ID-VG hysteresis curve. The retention property of MFISFET is examined by reading drain current after writing to the gate. The drain current as a function of retention time of MFISFET using NO layer remains almost the same value of its initial value over lo4 seconds at room temperature.
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