A high performance 1.5 V, 0.10 μm gate length CMOS technology with scaled copper metallization

Gilbert, P.; Yang, Il-Suk; Pettinato, C.; Angyal, M.; Boeck, B.; Fu, C.; VanGompel, T.; Tiwari, Ravi; Sparks, T.; Clark, William F.; Dang, Chien Mau; Mendonca, J.; Chu, Byung Hwan; Lucas, Kevin; Kling, Michael E.; Roman, Bernard J.; Park, E.; Huang, Fon-Shan; Woods, M.; Rose, Doug; McGuffin, K.; Nghiem, Anh; Banks, E.; McNelly, T.; Feng, Chaowen; Sturtevant, Julian M.; De, Han; Das, Amit K.; Veeraraghavan, S.; Nkansah, F.; Bhat, Mousumi

doi:10.1109/iedm.1998.746526

Cited by 10 publications

(7 citation statements)

References 4 publications

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“…Finally, if multiple resist technologies should become simultaneous options for fabrication, then exploiting the near-duality of the respective bright-and dark-field design problems (see Figure 9) could be of interest. 5 It is possible that, despite the obvious differences between the two types of technology, there are ways in which design and verification of alternating PSM may addressed independent of the bright or dark field perspective.…”

Section: Challenges For Psm Layout Design and Reuse-centric Methodolomentioning

confidence: 99%

“…Although this approach called for the use of negative photoresists, it was widely held that both layout design and mask manufacturing issues could be more readily solved in this case. On the other hand, most commercial applications of phase shifting, which use positive resists, have been based on bright field mask applications [5]. Although such methods have been applied in volume production, they continue to pose mask manufacturing problems that are yet unresolved.…”

Section: Phase-shifting Masksmentioning

confidence: 99%

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Subwavelength lithography and its potential impact on design and EDA

Kahng¹,

Pati²

1999

Proceedings of the 36th Annual ACM/IEEE Design Automation Conference

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This tutorial paper surveys the potential implications of subwavelength optical lithography for new tools and flows in the interface between layout design and manufacturability. We review control of optical process effects by optical proximity correction (OPC) and phase-shifting masks (PSM), then focus on the implications of OPC and PSM for layout synthesis and verification methodologies. Our discussion addresses the necessary changes in the designto-manufacturing flow, including infrastructure development in the mask and process communities, evolution of design methodology, and opportunities for research and development in the physical layout and verification areas of EDA.

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Section: Challenges For Psm Layout Design and Reuse-centric Methodolomentioning

confidence: 99%

Section: Phase-shifting Masksmentioning

confidence: 99%

Subwavelength lithography and its potential impact on design and EDA

Kahng¹,

Pati²

1999

Proceedings of the 36th Annual ACM/IEEE Design Automation Conference

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“…Although high-inductors have been demonstrated by using Al-interconnects [8], the best results so far were achieved with Cu-metallization [9]. The multi-level interconnect schemes of almost all advanced CMOS integration processes are based on Cu metallization [1], [10], [11]. A Cu top layer, on the other hand, does not provide a reliable bond-wire connection due to excessive Cu oxidation [12].…”

mentioning

confidence: 99%

Saddle Add-On Metallization for RF-IC Technology

Burghartz

Rejaei

Schellevis

2004

IEEE Trans. Electron Devices

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Abstract-A cost-effective add-on process module for reducing ohmic losses of radio-frequency (RF) inductors and interconnects in RF/BiCMOS and RF/CMOS technologies built on CMOS logic processes is proposed. The module is based on the local thickening of the top metal layer of the thin CMOS interconnects through copper (Cu) electroplating in selected areas. The combination of dense Cu-interconnects in the CMOS logic sections, of thick Cu top-level wiring through local Cu electroplating in the RF sections, and of aluminum (Al) capping of the bond pads provides an optimum tradeoff between packaging requirements, quality of passive components and interconnects, and cost. A special wet-etch process sequence for removal of the Cu-seed and adhesion films from the exposed top metal layer is described. A record quality factor of 13 for a 10-nH inductor on a conventional 5--cm silicon substrate is demonstrated.

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“…Fig. 7a; An enhanced breakdown in leakage current was observed when the stress was periodically interrupted (3 times in this case). Breakdown occurs less than 11000sec.…”

mentioning

confidence: 81%

“…Most recently, Motorola [3] announced a high performance lSV, 0 . 1 0~ gate length CMOS technology with Cu-low K (fluorinated oxide) dual damascene process, but no reliability data was revealed.…”

Section: Introductionmentioning

confidence: 99%