A new Ti salicide process featured by ~e-&norphizdtion before Ti film deposition and SEquential Two step sintering(PASET) has been proposed for sub-half micron CMOS. Pre-amorphization by As implantation can realize low and uniform sheet resistance TiSi2 on highly As doped n+ poly and diffusion layers with sub-half micron line width. Implanted As for pre-amorphization and sequential two step sintering prevents the TiSi2 overgrowth on p+ poly and diffusion layers. The PASET widens the process window in process integration. The resulting n-and p-MOSFETs show excellent characteristics. IntroductionSelf-aligned silicide(sa1icide) is one of the most important technologies for the realization of sub-half micron VLSI circuits with low series resistance in the poly and diffusion layers.However, the conventional Ti salicide process has the following difficulties. First, when the As concentration is increased to avoid the depletion layer formation in the poly gate, the sheet resistance of TiSi2 on As doped poly increases. Although the sheet resistance may be reduced by the high temperature sintering, the process window for this treatment is quite narrow. Because the overgrowth of TiSi2 on p+ regions is serious. Second, as is well known, the sheet resistance of TiSi2 on highly As doped poly increases, as line width decreases(1). This is the serious problem for VLSI devices with sub-half micron rule and beyond.Several proposals have been reported up to now to overcome the above mentioned difficulties. For example, Si ion beam mixing technique is effective to reduce the sheet resistance of TiSi2(2). However, Ti knock-on during Si ion implantation increases leakage current for shallow junctions. As another example, sequential deposition of Ti and amorphous Si is proposed to enhance the silicide reaction by avoiding the formation of the native oxide at Ti and Si interface(3). However, the process requires specifically designed equipment and would not be practical.This paper proposes a new salicide process;PASET. This technology produces TiSi2 with low sheet resistance even on fine line poly and diffusion layers, through wide process windows. CMOS devices with 0.3Spm rule are successfully developed by employing the PASET process technology.
It is difficult for LSIs to achieve simultaneously both low power consumption and high speed operation. While lowering supply voltage is an effective way of reducing dynamic power consumption, to maintain high speed under such conditions, it becomes necessary to reduce threshold voltage significantly, which will result in increased static power consumption. Furthermore, lowering both threshold and supply voltages increases the influence on static power consumption and on speed both of deviations in device parameters (such as gate length and channel dopant) and of variations in environmental factors (such as temperature and supply voltage). Previous approaches of dealing with these difficulties, include MOS transistors with triple-well structures and with multi-threshold voltages (i.e. the integration of high-Vt and low-Vt transistors on the same chip), but these require a high number of fabrication process steps, that significantly increase production costs [l, 2, 31.The elastic-Vt CMOS (EVTCMOS) circuit design illustrated in Figure 1 solves these problems by controlling MOS transistor source (not substrate) voltages, so fabrication requires no special steps. The post-fabrication threshold voltages can be switched back and forth between high Vt (sleep mode) and low Vt (active mode), and can be also controlled as means of reducing the sensitivity to device-parameter deviations and operating-environment variations. Figure 2 shows the power management unit.Vpin and Vnin can be varied without discharge (charge) of C2 and C3 when the mode is changed. This results in reduction of switching time between sleep and active modes, and in reduced static power consumption in sleep mode. At the same time, Vnn can be disconnected from (connected to) C1 so that the voltage difference between Vpp and Vnn can be stored (recalled).A deviation-compensated loop (DCL), shown in Figure 3, contains three types of replica circuits. For speed adjustment, the DCL contains a delay line (DL), the replica of a critical path contained in the EVTCMOS circuits. A phase detector (PD) and charge pumps (CPs) control the voltage level ofVpin andVnin so that the DL delay time equals the CLK period. Because this type of circuit suffers from an increased difference between rise and fall time (as a result of the reduced supply voltage, device-parameter deviations, and operating-environment variations), nMOS and PMOS delay line are added (NDLs and PDLs), composed of EVTCMOS inverters, to monitor the respective drive capabilities of the nMOS and PMOS transistors. NDLs have capacitors attached to their odd-numbered output terminals, PDLs to their even-numbered terminals. Additionally, a voltage regulator (VR), composed of a single nMOS or PMOS transistor, is immune to supply voltage fluctuation (PSRR: -35dB1, and phase-margin decrease (20" at 1GHz) in feed-back loops is negligible. Figure 4 shows simulated results for power management and the automatic deviation compensation process. In the active mode, i.e. when the amount of processing incurred by a load...
I n o r d e r t o p u r s u e h i g h s p e e d p e r f o r m a n c e o f CMOS l o g i c g a t e s , lpm CMOS technology has been r ealized by using advanced process technologies. CMOS l o g i c g a t e a r r a y s , w i t h minimum f e a t u r e s i z e o f 1 -l y m , were prepared, and their operation speed performances were evaluated. Delay times per gate o f 0.1 -0 . 2 ns have been observed i n CMOS l o g i c a r r a y s o f SNAND, 3NOR and F/0=3 INVERTER a r r a y s , o f 1 . l y n d e s i g n r u l e . CMOS basic technology has been developed. In this p a p e r , p r o c e s s t e c h n o l o g y , e l e c t r i c a l c h a r a c t e r i st i c s o f N-channel and P-channel transistors, and d e v i c e o p e r a t i o n c h a r a c t e r i s t i c s o f t h e CMOS l o g i c a r r a y s , a r e d e s c r i b e d .
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