High speed 1 µm CMOS technology

Abstract

I n o r d e r t o p u r s u e h i g h s p e e d p e r f o r m a n c e o f CMOS l o g i c g a t e s , lpm CMOS technology has been r ealized by using advanced process technologies. CMOS l o g i c g a t e a r r a y s , w i t h minimum f e a t u r e s i z e o f 1 -l y m , were prepared, and their operation speed performances were evaluated. Delay times per gate o f 0.1 -0 . 2 ns have been observed i n CMOS l o g i c a r r a y s o f SNAND, 3NOR and F/0=3 INVERTER a r r a y s , o f 1 . l y n d e s i g n r u l e . CMOS basic technology has been developed. In this p a p e r , p r o c e s s t e c h n o l o g y , e l e c t r i c a l c h a r a c t e r i st i c s o f N-channel and P-channel transistors, and d e v i c e o p e r a t i o n c h a r a c t e r i s t i c s o f t h e CMOS l o g i c a r r a y s , a r e d e s c r i b e d .

Electrical properties of CaxSr1−xBi2Ta2O9ferroelectric-gate field-effect transistors

“…Figures 12(a Interfacial layers (ILs) are found between the HAO layer and Si substrate. As previously reported, the main component of IL is SiO 2 [22]. The thickness of this SiO 2 -like IL increased with increase of T an .…”

Lowered operation voltage in Pt/SBi2Ta2O9/HfO2/Si ferroelectric-gate field-effect transistors by oxynitriding Si

“…In FeFETs, long-term data retention has been achieved by using metal/ ferroelectric/insulator/semiconductor (MFIS) structures of Pt/SrBi 2 Ta 2 O 9 (SBT)/(HfO 2 ) 0.75 (Al 2 O 3 ) 0.25 (HAO)/Si and Pt/SBT/HfO 2 /Si [4][5][6][7][8].…”

“…A 1 Author to whom any correspondence should be addressed. SiO x interfacial layer (IL) with a thickness of at least 3 nm grows between the insulator layer and the Si substrate when SBT structures are subjected to post-annealing at 800 • C for 1 h in an oxygen ambient for inducing ferroelectricity in SBT by polycrystallization [5,6,12]. IL formation leads to a decrease in the applied voltage because the dielectric constant of the IL (∼3.9) is considerably lower than that of SBT in a series MFIS capacitor.…”

Memory window widening of Pt/SrBi2Ta2O9/HfO2/Si ferroelectric-gate field-effect transistors by nitriding Si

“…The FeFETs with metalferroelectric-insulator-semiconductor structures of Pt/SrBi 2 Ta 2 O 9 (SBT)/(HfO 2 ) 0.75 (Al 2 O 3 ) 0.25 (HAO)/Si and Pt/SBT/ HfO 2 /Si realized a long-time retention characteristic [4][5][6][7][8]. The Pt/SBT/HAO/Si FeFETs have been intensively studied about their device reliability [4,9], threshold voltage controls [9][10][11] and HAO deposition condition optimizing [5,12]. New applications of the FeFETs to nonvolatile memory circuits have been also reported such as Fe-CMOS logic [13] and Fe-NAND flash memory [14].…”

“…Enough voltage to show a wide memory window should be applied to the SBT layer in an FeFET. However, growth of an SiO x interfacial layer (IL) between the insulator layer and the Si substrate significantly reduces the voltage applied to the ferroelectric SBT layer because the IL has a dielectric constant about 3.9 which is much smaller than that of the SBT in series [5,6,12]. The IL growth occurs during post-annealing usually at 800 Silicon nitride is known as an oxygen diffusion barrier with a higher dielectric constant than 3.9 and has been intensively studied as a gate dielectric of MOSFETs [15].…”