Graphene grown on a copper (Cu) substrate by chemical vapor deposition (CVD) is typically required to be transferred to another substrate for the fabrication of various electrical devices. PMMA-mediated wet process is the most widely used method for CVD-graphene-transfer. However, PMMA residue and wrinkles that inevitably remain on the graphene surface during the transfer process are critical issues degrading the electrical properties of graphene. In this paper, we report on a PMMA-mediated graphene-transfer method that can effectively reduce the density and size of the PMMA residue and the height of wrinkles on the transferred graphene layer. We found out that acetic acid is the most effective PMMA stripper among the typically used solutions to remove the PMMA residue. In addition, we observed that an optimized annealing process can reduce the height of the wrinkles on the transferred graphene layer without degrading the graphene quality. The effects of the suggested wet transfer process were also investigated by evaluating the electrical properties of field-effect transistors fabricated on the transferred graphene layer. The results of this work will contribute to the development of fabrication processes for high-quality graphene devices, given that the transfer of graphene from the Cu substrate is essential process to the application of CVD-graphene.

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The fabrication of oxide-based p−n heterojunctions that exhibit high rectification performance has been difficult to realize using standard manufacturing techniques that feature mild vacuum requirements, low thermal budget processing, and scalability. Critical bottlenecks in the fabrication of these heterojunctions include the narrow processing window of p-type oxides and the charge-blocking performance across the metallurgical junction required for achieving low reverse current and hence high rectification behavior. The overarching goal of the present study is to demonstrate a simple processing route to fabricate oxide-based p−n heterojunctions that demonstrate high on/off rectification behavior, a low saturation current, and a small turn-on voltage. For this study, room-temperature sputter-deposited p-SnO x and n-InGaZnO (IGZO) films were chosen. SnO x is a promising p-type oxide material due to its monocationic system that limits complexities related to processing and properties, compared to other multicationic oxide materials. For the n-type oxide, IGZO is selected due to the knowledge that postprocessing annealing critically reduces the defect and trap densities in IGZO to ensure minimal interfacial recombination and high charge-blocking performance in the heterojunctions. The resulting oxide p−n heterojunction exhibits a high rectification ratio greater than 10 3 at ±3 V, a low saturation current of ∼2 × 10 −10 A, and a small turn-on voltage of ∼0.5 V. In addition, the demonstrated oxide p−n heterojunctions exhibit excellent stability over time in air due to the p-SnO x with completed reaction annealing in air and the reduced trap density in n-IGZO.

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Carrier mobility is one of the most important parameters to evaluate the quality and uniformity of graphene. The mobility of graphene is typically extracted from the transconductance of a field-effect transistor fabricated with the graphene layer. However, the mobility value evaluated by this method is imprecise when the contact resistance is non-negligible, or the contact resistance is modulated by the gate bias, which is the case for typical graphene field-effect transistors. Here, we suggest a method for extracting the precise intrinsic field-effect mobility by considering the effective bias across the channel and its gate-induced modulation. We show that the contact resistances of typical graphene field-effect transistors are significantly modulated by gate bias and conventional methods can, therefore, cause a considerable error in the evaluation of the mobility. The proposed method in which the contact-induced error is removed gives a channel-length-independent intrinsic field-effect mobility. This method can be generally used to correctly evaluate the field-effect mobility of nano-scale or low-dimensional materials.

The overarching goal herein is to identify the factors dominating the performance of a‐IGZO‐based memristors. Despite the highest on/off ratio, greater than 104 with a preferred minimal set/reset bias achieved from a‐IGZO‐based memristors, it is observed that the switching performance and stability/reliability of the devices is significantly dominated by the VO·· density and metallization material, depending on their reactivity with IGZO. As the first governing factor, ensuring optimal VO·· concentration in the switching layer IGZO (VO··/OOx ratio 24.3% in this study) is crucial to obtain the tractable formation and rupture of conduction filament. Neither higher nor lower VO·· density than the optimized results in detrimental reliability issues, which may be ascribed to an uncontrollable filament in an abundant vacancy environment or a weak conducting path, respectively. As the second governing mechanism determining the memristor performance and reliability, it is suggested that metallization materials need to be carefully selected based on the thermodynamic redox potential and interfacial stability of the metallization material with IGZO. Metallization materials with larger reduction potential and interfacial stability are found to yield higher switching on/off ratio and greater device performance reliability.