Driven by malicious intent, attackers are impelled to extract the cipher key and thus compromise the cryptosystem through fault attacks. Existing fault-detection methods can effectively detect random faults in the cipher implementation, but yield a high fault bypass rate (FBR) under intelligent fault attacks. To address this limitation, we propose a new microarchitecture to thwart fault attacks that place mathematically symmetric faults on the two encryption data paths. To further reduce the FBR for a new lightweight cipher SIMON, we propose a new countermeasure that integrates operand permutation and masking techniques. Closed-form expressions for de-permutation and de-masking in SIMON are provided in this letter. Our method was assessed under two fault attack scenarios (random and symmetric fault injections) with bit-flip, stuck-at-0, and stuck-at-1 fault models. Simulation results show that our method minimizes the FBR to zero with the fault attack scenarios of symmetric fault location and stuck-at-0 fault injections. Overall, the proposed method outperforms the existing fault-detection methods in multiple fault attack conditions, at the cost of 5% more area overhead than the most hardware-efficient fault detection method. Index Terms-Block cipher, cryptography, fault attacks, fault bypass rate, fault detection, security, SIMON.
Soft errors caused by particle strikes are expected to increase as technology scales down. This is partially because more single-event transients (SET) are latched by memory elements at the primary output of combinational circuits. To speed up the assessment of SET-induced soft errors, we propose a systematic analysis method to examine the probability of a SET eventually being latched. In previous work, the latching probability of SET is only modeled as a function of SET pulse width and clock period. As soft error rate also strongly depends on other timing parameters, our novel analytical model additionally includes logic gate delays and setup/hold time of memory elements. In this work, a set of closed-form expressions for the latching probability are provided for various logic gate delays and SET pulse widths. Simulation results show that the soft error rate predicted by our model matches to that obtained from random simulations. The proposed systematic analysis method achieves up to 97% average accuracy, without using extensive Monte-Carlo simulation.
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