A Comprehensive FPGA-Based Assessment on Fault-Resistant AES against Correlation Power Analysis Attack

Dofe, Jaya; Pahlevanzadeh, Hoda; Yu, Qiaoyan

doi:10.1007/s10836-016-5598-9

Cited by 31 publications

(14 citation statements)

References 34 publications

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“…Advanced Encryption Standard (AES), also know as Rijndael, is the most popular encryption technique that researches have implemented in FPGAs, with 510 documents. These implementations have been made to increase the encryption speed [406][407][408][409][410], generate small footprint and cheap designs [167,411,412], test the encryption against fault injections/attacks [413,414] and to improve the fault detection/tolerance systems [366,415,416]. Elliptic Curve Cryptography (ECC) is increasingly used in practice to instantiate public-key cryptography protocols, based on the algebraic structure of elliptic curves over finite fields [417].…”

Section: Cryptography Techniquesmentioning

confidence: 99%

Field Programmable Gate Array Applications—A Scientometric Review

2019

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Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.

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Section: Cryptography Techniquesmentioning

confidence: 99%

Field Programmable Gate Array Applications—A Scientometric Review

2019

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“…In our work [35], we examined how hardware redundancy affects the crypto module's capability of resisting the power-based side-channel analysis attack. We used the accumulated partial guessing entropy (APGE)-sum of all PGE-as a metric to assess the speed of key retrieval.…”

Section: Information Redundancymentioning

confidence: 99%

Towards Energy-Efficient and Secure Computing Systems

Zhang

2018

JLPEA

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Countermeasures against diverse security threats typically incur noticeable hardware cost and power overhead, which may become the obstacle for those countermeasures to be applicable in energy-efficient computing systems. This work presents a summary of energy-efficiency techniques that have been applied in security primitives or mechanisms to ensure computing systems’ resilience against various security threats on hardware. This work also uses examples to discuss practical methods for securing the hardware for computing systems to achieve energy efficiency.

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“…Furthermore, algorithms can be classified as block and stream cipher algorithms based on the number of bits, and the algorithms can operate simultaneously [6][7][8][9][10]. Generally, these cryptographic algorithms are utilized in different applications such as banking applications, military and government [11], and critical infrastructures such as Smart Grid [12,13].…”

Section: Introductionmentioning

confidence: 99%

A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application

Kumar

Reddy²,

Rinaldi

et al. 2021

Electronics

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Nowadays, a huge amount of digital data is frequently changed among different embedded devices over wireless communication technologies. Data security is considered an important parameter for avoiding information loss and preventing cyber-crimes. This research article details the low power high-speed hardware architectures for the efficient field programmable gate array (FPGA) implementation of the advanced encryption standard (AES) algorithm to provide data security. This work does not depend on the look up tables (LUTs) for the implementation the SubBytes and InvSubBytes stages of transformations of the AES encryption and decryption; this new architecture uses combinational logical circuits for implementing SubBytes and InvSubBytes transformation. Due to the elimination of LUTs, unwanted delays are eliminated in this architecture and a subpipelining structure is introduced for improving the speed of the AES algorithm. Here, modified positive polarity reed muller (MPPRM) architecture is inserted to reduce the total hardware requirements, and comparisons are made with different implementations. With MPPRM architecture introduced in SubBytes stages, an efficient mixcolumn and invmixcolumn architecture that is suited to subpipelined round units is added. The performances of the proposed AES-MPPRM architecture is analyzed in terms of number of slice registers, flip flops, number of slice LUTs, number of logical elements, slices, bonded IOB, operating frequency and delay. There are five different AES architectures including LAES, AES-CTR, AES-CFA, AES-BSRD, and AES-EMCBE. The LUT of the AES-MPPRM architecture designed in the Spartan 6 is reduced up to 15.45% when compared to the AES-BSRD.

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A Comprehensive FPGA-Based Assessment on Fault-Resistant AES against Correlation Power Analysis Attack

Cited by 31 publications

References 34 publications

Field Programmable Gate Array Applications—A Scientometric Review

Field Programmable Gate Array Applications—A Scientometric Review

Towards Energy-Efficient and Secure Computing Systems

A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application

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