We have fabricated GeO2∕Ge metal-oxide-semiconductor (MOS) structures by direct thermal oxidation of Ge substrates. The interface trap density (Dit) of Al∕GeO2∕Ge MOS structures, measured by the low temperature conductance method including the effect of the surface potential fluctuation, is found to be reduced as the oxidation temperature increases. The minimum values of Dit can be obtained for the oxidation around 575°C, which is in the maximum temperature range where GeO volatilization does not occur under atmospheric pressure of O2. It is also found that the hydrogen annealing before Al gate formation is effective for the passivation of GeO2∕Ge interface states. It is clarified, as a result, that the minimum Dit value lower than 1011cm−2eV−1 can be obtained for GeO2∕Ge MOS interfaces fabricated by direct oxidation of Ge substrates.

We demonstrate the enhancement of hole mobility in an ultrathin Si/Ge/Si-on-insulator (SOI) channel metal-oxidesemiconductor field-effect transistor (MOSFET) with a metal source and drain (S/D). The ultrathin Si/Ge structure is fabricated on a SOI substrate by low-temperature molecular-beam epitaxy (LTMBE). We examined the impact of the Si/Ge/ Si structural parameters and the crystal quality on the electrical characteristics of MOSFETs, particularly from the viewpoints of the Ge thickness and the annealing temperature. As a result, the hole mobility of the fabricated Ge-on-insulator (GOI)-pMOSFETs after annealing at 600 C was found to be 1.2 times larger than the Si universal hole mobility. For the Ge thickness dependence of hole mobility, the MOSFETs with the Ge thicknesses of 8, 12, and 16 nm had almost the same mobility. On the other hand, the sample with 4 nm Ge thickness had lower mobility. For the annealing temperature dependence, the hole mobility had a maximum value at 600 C and decreased with increasing annealing temperature above 700 C.

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Histochemical demonstration of glycogen the medium added sodium sulfate,but is not demonstrable in the Takeuchi medium.

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