A methodology for testing active MCM silicon-based substrates by using boundaly scan elements integrated into the carrier is presented. By optimizing the scan cell organization, the test circuitry causes no degradation of signal propagation. Tests of the bare substrate and of the assembled cam'er can be accomplished ejjiciently. To monitor substrate and chip temperature, an on-line monitoring system is integrated into the substrate. The 0 stem is compensated for supply voltage variations and is calibrated to offset fabrication process deviations. A n experimental cam'er is fabricated.
In this paper we will describe a solution to test I/O cells that use four level pulse amplitude modulation (PAM-4) at data rates of 32 Gbaud using a commercial ATE platform without any external instruments. The solution is based on an active test fixture where a retimed digital to analog converter (DAC) is used to generate the PAM-4 stimulus signaling. The comparator side is implemented using a single differential comparator and three consecutive functional tests with different patterns and compare threshold voltages.
A MCM test strategy using boundary scan-cells integrated into silicon substrates is presented. The differences between IC-based boundary scan and active substrate boundary scan and their eflects on scan-cell placement and design are highlighted. A yield optimized partition of the test circuitry and an adaption to commercially available boundary scan testsystems is proposed. Active substrates with boundary scan test capabilities are fabricated based on the identified requirements. The adaption to the test system is evaluated.
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