An Active Test Fixture Approach for 40 Gbps and Above At-Speed Testing Using a Standard ATE System

Moreira, Jose; Roth, Bernhard; Werkmann, H.; Klapproth, Lars; Howieson, Michael; Broman, Mark; Ouedraogo, Wend; Lin, Meng

doi:10.1109/ats.2013.57

Cited by 6 publications

(11 citation statements)

References 5 publications

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“…These MUX modules use in turn two 16 Gbps ATE channels each. The MUXes' retiming clock is generated from an ATE channel and a clock quadrupling circuit that has already been described in [4,5]. The retimed DAC also needs a retiming clock which is also generated from an ATE channel using an x8 frequency multiplication circuit.…”

Section: The Pam-4 Integrated Ate Solutionmentioning

confidence: 99%

“…The critical new component of this solution compared to what was presented in [4,5,6] is the retimed DAC module that is used to generate the PAM-4 waveform.…”

Section: Introductionmentioning

confidence: 99%

“…In this paper we will follow the approach presented in [4,5,6] but with the required changes to support 32 Gbaud PAM-4 signaling.…”

Section: Introductionmentioning

confidence: 99%

“…In [4,5,6,7] different solutions for testing NRZ I/O running at data rates of 32 Gbps and above using a commercial ATE were presented. In this paper we will follow the approach presented in [4,5,6] but with the required changes to support 32 Gbaud PAM-4 signaling.…”

Section: Introductionmentioning

confidence: 99%

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An ATE Based 32 Gbaud PAM-4 At-Speed Characterization and Testing Solution

Moreira

Werkmann

Ishida

et al. 2014

2014 IEEE 23rd Asian Test Symposium

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In this paper we will describe a solution to test I/O cells that use four level pulse amplitude modulation (PAM-4) at data rates of 32 Gbaud using a commercial ATE platform without any external instruments. The solution is based on an active test fixture where a retimed digital to analog converter (DAC) is used to generate the PAM-4 stimulus signaling. The comparator side is implemented using a single differential comparator and three consecutive functional tests with different patterns and compare threshold voltages.

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Section: The Pam-4 Integrated Ate Solutionmentioning

confidence: 99%

“…The critical new component of this solution compared to what was presented in [4,5,6] is the retimed DAC module that is used to generate the PAM-4 waveform.…”

Section: Introductionmentioning

confidence: 99%

“…In this paper we will follow the approach presented in [4,5,6] but with the required changes to support 32 Gbaud PAM-4 signaling.…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An ATE Based 32 Gbaud PAM-4 At-Speed Characterization and Testing Solution

Moreira

Werkmann

Ishida

et al. 2014

2014 IEEE 23rd Asian Test Symposium

Self Cite

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“…Low frequency energy present in a transmission line will interfere with highly attenuated energy from the high frequency domain causing intersymbol interference (ISI). In practice, it has been demonstrated that for better synthesis of a device, networks with equalizer (EQ) are positioned in the test fixture as presented in [4]. Jitter histogram, time, and frequency characteristics are more accurate in this case.…”

Section: Introductionmentioning

confidence: 99%

Passive Equalization Networks—Efficient Synthesis Approach for High-Speed Signal Integrity Characterization

Brinaru

2021

Sensors

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High data rates challenges and long traces from current state-of-the-art systems imply high attenuation. In the present article, we will present a detailed process of synthesis of equalizers, for choosing the correct one for a given application. The methods are based on scattering parameters applied on interconnections modeled as microstrip or stripline. Firstly, one may have an overview of types of equalizers, passive, active, and adaptive ones, and a detailed filter synthesis is applied in microwave systems having as start point the insertion loss of a given trace on a given substrate. Next, time domain analyses offer a better understanding of the performance of the interconnect, based on eye diagram inspection and the variation of waveforms with time. Finally, we will present results based on simulation of the equalizers network in a microstrip technology followed by discussions and conclusions. The study proposes to use equalizers in either the transmitter or receiver point, proposes a bridge equalizer with the cost of additional elements but improved constant input, output impedance, and also a new variant for single ended trace based on microwave resonator is proposed. Performance is demonstrated by results from simulations.

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An Ultra-High-Speed Test Module and FPGA-Based Development Platform

Chen

Keezer

2016

2016 IEEE 25th Asian Test Symposium (ATS)

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An Active Test Fixture Approach for 40 Gbps and Above At-Speed Testing Using a Standard ATE System

Cited by 6 publications

References 5 publications

An ATE Based 32 Gbaud PAM-4 At-Speed Characterization and Testing Solution

An ATE Based 32 Gbaud PAM-4 At-Speed Characterization and Testing Solution

Passive Equalization Networks—Efficient Synthesis Approach for High-Speed Signal Integrity Characterization

An Ultra-High-Speed Test Module and FPGA-Based Development Platform

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