A simple and easy to implement method for direct on-chip capacitance measurements has been developped. It aims to both, to reduce the requirements for measurement equipment as well as to avoid area-consuming special structures for the determination of capacitance parameters. The capacitance measurement is achieved by a measurement of the time averaged current from avoltage source. The minimum size of measurable capacitances is in the range of the minimum drain capacitance of a transistor and can therefore be scaled with the technology. The on-chip teststructure for the measurement consists of only two transistors connected to the capacitance.
A methodology for testing active MCM silicon-based substrates by using boundaly scan elements integrated into the carrier is presented. By optimizing the scan cell organization, the test circuitry causes no degradation of signal propagation. Tests of the bare substrate and of the assembled cam'er can be accomplished ejjiciently. To monitor substrate and chip temperature, an on-line monitoring system is integrated into the substrate. The 0 stem is compensated for supply voltage variations and is calibrated to offset fabrication process deviations. A n experimental cam'er is fabricated.
A MCM test strategy using boundary scan-cells integrated into silicon substrates is presented. The differences between IC-based boundary scan and active substrate boundary scan and their eflects on scan-cell placement and design are highlighted. A yield optimized partition of the test circuitry and an adaption to commercially available boundary scan testsystems is proposed. Active substrates with boundary scan test capabilities are fabricated based on the identified requirements. The adaption to the test system is evaluated.
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