Experimental plasma etching apparatus and methods u t i l i z i n g BC.13 etch gas have been developed f o r t h e a c c u r a t e p a t t e r n i n g of t h i n A 1 and A1-Si a l l o y m e t a l l i z a t i o n as used i n i n t e g r a te d c i r c u i t f a b r i c a t i o n . A two micron linewidth capability has been achieved for the patterning of 0.5 micron thick m e t a l l i z a t i o n on three inch diameter wafers with p o s i t i v e a n d n e g a t i v e p h o t o r e s i s t e t c h masks as t h i n as 25008. Etchrates of 500 t o 1000 8/min. are t y p i c a l , and t h e r e i s n e g l i g i b l e e t c h i n g of b o t h t h e p h o t o r e s i s t and the underlying Si02 l a y e r s . The process is CMOS compatible, yielding threshold voltage shift and temperature-bias s t a b i l i t y s p e c i f i c a t i o n s o f less than 20.050 v o l t s t h a t a r e c o m p a r a b l e t o t h o s e f o r wet chemically etched devices.

In this article, we present the results of a study initiated to improve the step coverage of phosphosilicate glass (PSG) obtained with a low temperature LPCVD process and intended for use in VLSI multilevel interconnect structures. It is shown that increasing the PSG film thickness leads to a substantial improvement in the PSG step‐coverage profile, but could create problems for subsequent patterning steps. We have alleviated these problems through the use of dry etching to reduce the thickness of these films to values more compatible with VLSI multilevel interconnect technology, while successfully maintaining the superior step‐coverage profile obtained with the thicker PSG films.

Thin film transistors (TFTs) are of current interest for addressing large-area flat panel displays. In most cases, in-vacuum mechanical masking and successive evaporations in a single pumpdown have been used to define the necessary patterns. While this has the advantage of minimizing contamination of the film interfaces, complex and expensive equipment is needed to fabricate high resolution patterns over large areas. We have, therefore, investigated the use of conventional vacuum deposition and photoengraving processes, similar to those used in silicon integrated circuit technology, and have successfully fabricated CdSe TFTs in which the gate and source-drain levels have been defined by photoengraving. Al and Cr metallizations and Al2O3 dielectric layers have been used. Well-saturated transistors with switching ratios of ∠104 and electron mobilities of ∠50 cm2 V−1 s−1 are achieved only after the fabricated structure is thermally annealed. Since some thermal annealing appears to be essential in all of the reported TFT processes, the physical significance of thermal annealing has been investigated. A model involving activated diffusion is presented and the effect of different annealing conditions on transistor characteristics discussed.

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