Oxygen microwave (mW) plasmas have been used to strip AZ 1350 J photoresist on glass substrates and to decapsulate hybrid resistor networks and Si IC packages. It has been found that the use of microwaves as the generating field provides an abundance of long‐lived atomic oxygen such that processing can be carried out in the afterflow of the discharge. In this downstream system, photoresist and organically based epoxy encapsulants were removed at rates of approximately 6.0 μm/min. In addition, optical emission spectroscopy, from the O2 plasma and the chemiluminescence in the processing zone, has been used to characterize the system.

This paper presents results on the effects of sintering temperature, sintering time, and contact geometry on Al/Si and Al/poly‐Si contact resistance. At sintering temperatures >450°C the resistance of p‐type contacts is virtually constant and independent of time. The resistance of n‐type contacts, particularly to poly‐Si, increases with increasing sintering temperature for T>450°C . This is attributed to the precipitation of a p‐type (Al‐doped) layer on n‐contacts during sintering. The interface resistance of both Al/Si and Al/poly‐Si contacts is independent of the length of the contact and inversely proportional to the width of the contact.

In this article, we present the results of a study initiated to improve the step coverage of phosphosilicate glass (PSG) obtained with a low temperature LPCVD process and intended for use in VLSI multilevel interconnect structures. It is shown that increasing the PSG film thickness leads to a substantial improvement in the PSG step‐coverage profile, but could create problems for subsequent patterning steps. We have alleviated these problems through the use of dry etching to reduce the thickness of these films to values more compatible with VLSI multilevel interconnect technology, while successfully maintaining the superior step‐coverage profile obtained with the thicker PSG films.

This paper presents results on the use of an optical spectroscopic system in the study of reactive ion beam etching (RIBE) of Si wafers and Al thin films deposited on glass substrates. Ion beams derived from Ar, CF4, and CCl4 gases have been used at energies in the range of 0.3–1.7 keV. The emission of ultraviolet and visible photons from sputtered excited substrate particles has been observed. Of particular interest was the detection of SiF and AlCl excited molecules during RIBE of Si and Al substrates, respectively. The effects of ion energy to ion current, and the presence of residual O2 in the etching chamber have been investigated. The results, analyzed on the basis of existing sputtering theories, indicate that at energies below ?500 eV, RIBE is mainly characterized by the sputtering of molecules adsorbed on the bombarded surface. At higher energies, the etching is dominated by the sputtering of elemental atomic species. The addition of small amounts of O2 to the etch chamber was found to enhance the etch rate of both Si and Al substrates. This has been attributed to the removal of a carbonaceous layer formed on the substrate surface as a result of ion-impact dissociation of the bombarding species.

This paper presents results on rapid isothermal fusion (RIF) characteristics of phosphosilicate glass (PSG) obtained using an incoherent lamp annealer in a N2 ambient. The effects of varying the temperature (10007-1200~ the cycle duration (10-60s), and the phosphorus concentration in the glass (2.5-8.0 w/o) were investigated. The out-diffusion of phosphorus from the PSG films during RIF cycles were also studied. In conjunction with these experiments, dopant redistribution induced by typical RIF cycles in a boron-implanted silicon substrate was measured to assess the practicality of the RIF technique for VLSI applications and to identify a process window. The results for the boron profile redistribution were used as a basis of comparison between RIF and conventional furnace treatments. Although restricted to VLSI applications where a relatively high phosphorus content of approximately 8 w/o is acceptable in PSG films, it is concluded that RIF in a N~ ambient is nevertheless much more effective for the fusion of PSG films than conventional furnace processing and thus much more compatible with VLSI processing.As a part of the fabrication sequence for integrated circuits, a layer of phosphosilicate glass (PSG) is deposited to provide passivation and electrical insulation between metal interconnects and underlying structures. Before the subsequent deposition of metal takes place, it is necessary to smooth the surface topography to ensure continuity of the overlying metallization. At present, this treatment is typically a furnace glass fusion cycle at 1000~ for 30 min or more (1-5) and is the last high temperature process step in the fabrication of LSIC's. This heavy thermal load will be unacceptable for processing new generations of VLSI circuits because it will induce appreciative lateral and vertical dopant redistribution in small geometry devices.Thermal processing requirements can be eased by using different materials or ambients during the fusion cycle. Although increasing the phosphorus concentration does lead to a lower fusion temperature for PSG films, excessive concentrations eventually promote the formation of phosphoric acid in the presence of moisture (2, 4), thereby causing reliability problems due to corrosion of overlying aluminum interconnect lines. As an alternative solution, rapid isothermal fusion (RIF) has been shown in limited studies to improve PSG step coverage, while causing less junction diffusion than conventional furnace processing cycles because of its lower time-temperature product (6-9).In this work, we have studied the effect of RIF on PSG films having a practical range of phosphorus concentrations, namely, 2.5, 4.0, 6.6, and 8.0 w/o. The RIF experiments were performed in a N.2 ambient using a tungsten halogen lamp system. :~ In addition, the out-diffusion of phosphorus from the PSG films during RIF was examined.The amount of dopant diffusion induced by RIF in underlying device junction areas will largely determine its range of usefulness for VLSI applications (6-12). There-* Electrochem...