Articles you may be interested inFabrication of polyimide sacrificial layers with inclined sidewalls based on reactive ion etching AIP Advances 4, 031328 (2014); 10.1063/1.4868379 Fabrication and characterization of In Ga As P ∕ In P double shallow-ridge rectangular ring laser photonic integration circuits by cascade reactive ion etching/inductively coupled plasma etching J. Vac. Sci. Technol. B 26, L23 (2008); 10.1116/1.2839882 Study of the impact of the time-delay effect on the critical dimension of a tungsten silicide/polysilicon gate after reactive ion etching Etch rate control in a 27 MHz reactive ion etching system for ultralarge scale integrated circuit processingPolysilicides currently find great interest as low resistivity gate and interconnect materials for integrated MaS circuits. We report on detailed investigations of the dry etching characteristics of Ta-silicideln+ -poly-Si double layers in fluorine and chlorine containing gases. A batch-type parallel plate reactor operated in RIE mode is used. We find a sensitive dependence of the etching results on various process parameters, such as gas mixtures, pressure, and rf power. Possible mechanisms for these findings are discussed. Anisotropic etching of the double layer has been achieved using a two stage process. In addition, we analyze the influence of the layer preparation technique on etching profiles.
Mobility universality, confirmed for long-channel metal–oxide–semiconductor field-effect transistors (MOSFETs), is demonstrated to be preserved for scaled MOSFET technologies down to 100 nm gate length, although phenomena such as quantum-mechanical and poly-silicon depletion effects play important roles. This result was obtained by applying a compact model based on the drift-diffusion approximation and relying only on Ids–Vgs measurements instead of using a conventional method with supplemental Cgate–Vgs measurements. It is confirmed that the carrier mobility is still governed by the electric field applied, and that the drift-diffusion approximation remains valid down to channel length of 100 nm. Consequently, the carrier behavior of such scaled small-size MOSFETs can be precisely described by simple analytical equations, which is important for the development of efficient circuit-simulation models.
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