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The circuit simulation model Hiroshima-university STARC IGFET Model silicon-on-insulator (HiSIM-SOI) for the fully depleted SOI metal-oxide-semiconductor field-effect-transistor (MOSFET) is developed based on the surafce-potential description. To include all device features of the SOI-MOSFET explicitly, the surface potential values not only at the SOI surface but also the back side, as well as the bulk back-gate are solved iteratively. The total iteration for the potential calculation requires only about twice as much calculation time as the bulk-MOSFET case, solving ony at the surface. The model reproduces measured I-V characteristics within numerical accuracy, and is proved stable circuit convergence.

We have developed a fully-depleted SOI-MOSFET model HiSIM-SOI for circuit simulation by solving the potential distribution along all three important SOI-surfaces selfconsistently. Besides comparison to measured I-V data, the model is verified with 1/f noise analysis, sensitive to the carrier concentration and distribution along the channel. The carrier concentration increase, due to confinement of the silicon layer, results in enhanced 1/f noise in comparison with the bulk-MOSFET. Our results show that further reduction of the silicon-layer thickness for achieving higher driving capability will cause unavoidable enhancement of the noise.

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